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| 8271g?avr?02/2013 features ? high performance, low power atmel ? avr ? 8-bit microcontroller family ? advanced risc architecture ? 131 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 20 mips throughput at 20mhz ? on-chip 2-cycle multiplier ? high endurance non-volatile memory segments ? 4/8/16/32kbytes of in-system self-programmable flash program memory ? 256/512/512/1kbytes eeprom ? 512/1k/1k/2kbytes internal sram ? write/erase cycles: 10 ,000 flash/100,000 eeprom ? data retention: 20 years at 85 ? c/100 years at 25 ? c (1) ? optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-write operation ? programming lock for software security ? atmel ? qtouch ? library support ? capacitive touch buttons, sliders and wheels ? qtouch and qmatrix ? acquisition ? up to 64 sense channels ? peripheral features ? two 8-bit timer/counters with separate prescaler and compare mode ? one 16-bit timer/counter with separate prescaler, compare mode, and capture mode ? real time counter with separate oscillator ? six pwm channels ? 8-channel 10-bit adc in tqfp and qfn/mlf package temperature measurement ? 6-channel 10-bit adc in pdip package temperature measurement ? programmable serial usart ? master/slave spi serial interface ? byte-oriented 2-wire serial interface (philips i 2 c compatible) ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? interrupt and wake-up on pin change ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibrated oscillator ? external and internal interrupt sources ? six sleep modes: idle, adc noise reduction, power-save, power-down, standby, and extended standby ? i/o and packages ? 23 programmable i/o lines ? 28-pin pdip, 32-lead tqfp, 28-pad qfn/mlf and 32-pad qfn/mlf ? operating voltage: ? 1.8 - 5.5v ? temperature range: ?-40 ? c to 85 ? c ? speed grade: ? 0 - 4mhz@1.8 - 5.5v, 0 - 10mhz@2.7 - 5.5.v, 0 - 20mhz @ 4.5 - 5.5v ? power consumption at 1mhz, 1.8v, 25 ? c ? active mode: 0.2ma ? power-down mode: 0.1a ? power-save mode: 0.75a (including 32khz rtc) atmel 8-bit microcontroller with 4/8/16/32kbytes in-system programmable flash atmega48a; atmega48pa; atmega88a; atmega88pa; atmega168a; atmega168pa; atmega328; atmega328p
2 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 1. pin configurations figure 1-1. pinout atmega48a/pa/ 88a/pa/168a/pa/328/p 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 (pcint19/oc2b/int1) pd3 (pcint20/xck/t0) pd4 gnd vcc gnd vcc (pcint6/xtal1/tosc1) pb6 (pcint7/xtal2/tosc2) pb7 pc1 (adc1/pcint9) pc0 (adc0/pcint8) adc7 gnd aref adc6 avcc pb5 (sck/pcint5) 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 (pcint21/oc0b/t1) pd5 (pcint22/oc0a/ain0) pd6 (pcint23/ain1) pd7 (pcint0/clko/icp1) pb0 (pcint1/oc1a) pb1 (pcint2/ss/oc1b) pb2 (pcint3/oc2a/mosi) pb3 (pcint4/miso) pb4 pd2 (int0/pcint18) pd1 (txd/pcint17) pd0 (rxd/pcint16) pc6 (reset/pcint14) pc5 (adc5/scl/pcint13) pc4 (adc4/sda/pcint12) pc3 (adc3/pcint11) pc2 (adc2/pcint10) 32 tqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 (pcint14/reset) pc6 (pcint16/rxd) pd0 (pcint17/txd) pd1 (pcint18/int0) pd2 (pcint19/oc2b/int1) pd3 (pcint20/xck/t0) pd4 vcc gnd (pcint6/xtal1/tosc1) pb6 (pcint7/xtal2/tosc2) pb7 (pcint21/oc0b/t1) pd5 (pcint22/oc0a/ain0) pd6 (pcint23/ain1) pd7 (pcint0/clko/icp1) pb0 pc5 (adc5/scl/pcint13) pc4 (adc4/sda/pcint12) pc3 (adc3/pcint11) pc2 (adc2/pcint10) pc1 (adc1/pcint9) pc0 (adc0/pcint8) gnd aref avcc pb5 (sck/pcint5) pb4 (miso/pcint4) pb3 (mosi/oc2a/pcint3) pb2 (ss/oc1b/pcint2) pb1 (oc1a/pcint1) 28 pdip 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 32 mlf top view (pcint19/oc2b/int1) pd3 (pcint20/xck/t0) pd4 gnd vcc gnd vcc (pcint6/xtal1/tosc1) pb6 (pcint7/xtal2/tosc2) pb7 pc1 (adc1/pcint9) pc0 (adc0/pcint8) adc7 gnd aref adc6 avcc pb5 (sck/pcint5) (pcint21/oc0b/t1) pd5 (pcint22/oc0a/ain0) pd6 (pcint23/ain1) pd7 (pcint0/clko/icp1) pb0 (pcint1/oc1a) pb1 (pcint2/ss/oc1b) pb2 (pcint3/oc2a/mosi) pb3 (pcint4/miso) pb4 pd2 (int0/pcint18) pd1 (txd/pcint17) pd0 (rxd/pcint16) pc6 (reset/pcint14) pc5 (adc5/scl/pcint13) pc4 (adc4/sda/pcint12) pc3 (adc3/pcint11) pc2 (adc2/pcint10) note: bottom pad should be soldered to ground. 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 28 mlf top view (pcint19/oc2b/int1) pd3 (pcint20/xck/t0) pd4 vcc gnd (pcint6/xtal1/tosc1) pb6 (pcint7/xtal2/tosc2) pb7 (pcint21/oc0b/t1) pd5 (pcint22/oc0a/ain0) pd6 (pcint23/ain1) pd7 (pcint0/clko/icp1) pb0 (pcint1/oc1a) pb1 (pcint2/ss/oc1b) pb2 (pcint3/oc2a/mosi) pb3 (pcint4/miso) pb4 pd2 (int0/pcint18) pd1 (txd/pcint17) pd0 (rxd/pcint16) pc6 (reset/pcint14) pc5 (adc5/scl/pcint13) pc4 (adc4/sda/pcint12) pc3 (adc3/pcint11) pc2 (adc2/pcint10) pc1 (adc1/pcint9) pc0 (adc0/pcint8) gnd aref avcc pb5 (sck/pcint5) note: bottom pad should be soldered to ground. table 1-1. 32ufbga - pinout atmega48a/48pa/88a/88pa/168a/168pa 123456 a pd2 pd1 pc6 pc4 pc2 pc1 b pd3 pd4 pd0 pc5 pc3 pc0 c gnd gnd adc7 gnd d vdd vdd aref adc6 e pb6 pd6 pb0 pb2 avdd pb5 f pb7 pd5 pd7 pb1 pb3 pb4 3 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 1.1 pin descriptions 1.1.1 vcc digital supply voltage. 1.1.2 gnd ground. 1.1.3 port b (pb7:0) xtal1/xtal2/tosc1/tosc2 port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buf- fers have symmetrical drive ch aracteristics with both high si nk and source capability. as i nputs, port b pins that are externally pulled low will source current if the pull-up resistor s are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. depending on the cl ock selection fuse settings, pb6 can be used as input to the in verting oscillator amplifier and input to the internal clock operating circuit. depending on the clock selection fuse settings, pb7 can be used as output fr om the inverting o scillator amplifier. if the internal calibrated rc oscillator is used as chip clock source, pb7...6 is used as tosc2...1 input for the asynchronous timer/counter2 if the as2 bit in assr is set. the various special features of port b are elaborated in ?alternate functions of port b? on page 83 and ?system clock and clock options? on page 26 . 1.1.4 port c (pc5:0) port c is a 7-bit bi-directional i/o port with internal pull- up resistors (selected for each bit). the pc5...0 output buf- fers have symmetrical drive characteristi cs with both high sink and source capability. as input s, port c pins that are externally pulled low will source current if the pull-up resistors are activate d. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. 1.1.5 pc6/reset if the rstdisbl fuse is programmed, pc6 is used as an i/o pin. note that the electrical characteristics of pc6 dif- fer from those of the other pins of port c. if the rstdisbl fuse is unprogrammed, pc6 is used as a reset input. a low level on th is pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in table 29-16 on page 312 . shorter pulses are not guaranteed to generate a reset. the various special features of port c are elaborated in ?alternate functions of port c? on page 86 .| 1.1.6 port d (pd7:0) port d is an 8-bit bi-directional i/o port with internal pull- up resistors (selected for each bit). the port d output buf- fers have symmetrical drive characteristi cs with both high sink and source capability. as input s, port d pins that are externally pulled low will source current if the pull-up resistors are activate d. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. the various special features of port d are elaborated in ?alternate functions of port d? on page 89 . 1.1.7 av cc av cc is the supply voltage pin for the a/d converter, pc3:0, and adc7:6. it should be externally connected to v cc , even if the adc is not used. if the ad c is used, it should be connected to v cc through a low-pass filter. note that pc6...4 use digital supply voltage, v cc . 4 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 1.1.8 aref aref is the analog reference pin for the a/d converter. 1.1.9 adc7:6 (tqfp and qfn/mlf package only) in the tqfp and qfn/mlf package, adc7:6 serve as anal og inputs to the a/d conver ter. these pins are powered from the analog supply and serve as 10-bit adc channels. 5 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 2. overview the atmega48a/pa/88a/pa/168a/pa/328/p is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the atmega48a/pa/88a/pa/168a/pa/ 328/p achieves throughputs approach ing 1 mips per mhz allowing the system designer to optimize power consumption versus processing speed. 2.1 block diagram figure 2-1. block diagram the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the result ing architecture is more c ode efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. port c (7) port b (8) port d (8) usart 0 8bit t/c 2 16bit t/c 1 8bit t/c 0 a/d conv. internal bandgap analog comp. spi twi sram flash eeprom watchdog oscillator watchdog timer oscillator circuits / clock generation power supervision por / bod & reset vcc gnd program logic debugwire 2 gnd aref avcc data b u s adc[6..7] pc[0..6] pb[0..7] pd[0..7] 6 reset xtal[1..2] cpu 6 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 the atmega48a/pa/88a/pa/168a/pa/328/p provides the fo llowing features: 4k/8kbytes of in-system program- mable flash with read-while-write capabilities, 256/ 512/512/1kbytes eeprom, 512/1k/1k/2kbytes sram, 23 general purpose i/o lines, 32 general purpose working regist ers, three flexible timer/counters with compare modes, internal and external interrupts, a serial programmable usart, a byte-oriented 2-wire serial interface, an spi serial port, a 6-channel 10-bit adc (8 channels in tqfp and qfn/mlf packages), a programmable watchdog timer with internal oscillator, and five software selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, usart, 2-wire se rial interface, spi port, and interrupt system to con- tinue functioning. the power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. in power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while th e rest of the device is sleeping. the adc noise reduction mode stops the cpu and all i/o modules except asynchrono us timer and adc, to minimize switching noise during adc conversions. in standby mode, the crystal/r esonator oscillator is running while the rest of th e device is sleep- ing. this allows very fast start-up combined with low power consumption. atmel ? offers the qtouch ? library for embedding capacitive touch buttons, sliders and wheels functionality into avr ? microcontrollers. the patented charge-tr ansfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes adjacent key suppression ? (aks ? ) technology for unambiguous detection of key events. the easy-to-use qtouch suite toolchain allows you to explore, develop and debug your own touch applications. the device is manufactured using atmel?s high density non- volatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface, by a conventional non- volatile memory programmer, or by an on-chip boot program running on the avr core. the boot program can use any interface to download the application program in the application flash memory. software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write opera- tion. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel atmega48a/pa/88a/pa/168a/pa/328/p is a powerful microcontroller that provides a highly flexible and cost effec- tive solution to many embedded control applications. the atmega48a/pa/88a/pa/168a/pa/328/p avr is supported with a full suite of program and system develop- ment tools including: c compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 2.2 comparison between processors the atmega48a/pa/88a/pa/168a/pa/328/p differ only in memory sizes, boot loader support, and interrupt vector sizes. table 2-1 summarizes the different memory and interrupt vector sizes for the devices. atmega48a/pa/88a/pa/168a/pa/328/p support a real read-while-write self-programming mechanism. there is a separate boot loader section, and the spm instruction can only execute from there. in atmega 48a/48pa there table 2-1. memory size summary device flash eeprom ram interrupt vector size atmega48a 4kbytes 256bytes 512bytes 1 instruction word/vector atmega48pa 4kbytes 256bytes 512bytes 1 instruction word/vector atmega88a 8kbytes 512bytes 1kbytes 1 instruction word/vector atmega88pa 8kbytes 512bytes 1kbytes 1 instruction word/vector atmega168a 16kbytes 512bytes 1kbytes 2 instruction words/vector atmega168pa 16kbytes 512bytes 1kbytes 2 instruction words/vector atmega328 32kbytes 1kbytes 2kbyte s 2 instruction words/vector atmega328p 32kbytes 1kbytes 2kbytes 2 instruction words/vector 7 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 is no read-while-write support and no separate boot loader section. the spm instruction can execute from the entire flash 3. resources a comprehensive set of development tools, applicati on notes and datasheets are available for download on http://www.atmel.com/avr. note: 1. 4. data retention reliability qualification re sults show that the projected data retention fa ilure rate is much less than 1 ppm over 20 years at 85c or 100 years at 25c. 5. about code examples this documentation contains simple code examples that br iefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documentation for more details. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructions that allow access to ex tended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. 6. capacitive touch sensing the atmel ? qtouch ? library provides a simple to use solution to realize touch sens itive interfaces on most atmel avr ? microcontrollers. the qtouch library includes support for the atmel qtouch and atmel qmatrix ? acquisition methods. touch sensing can be added to any application by linki ng the appropriate atmel qtouch library for the avr micro- controller. this is done by using a si mple set of apis to define the touch ch annels and sensors, and then calling the touch sensing api?s to retrieve the channel information and determine the touch sensor states. the qtouch library is free and downloadable from the atmel website at the following location: www.atmel.com/qtouchlibrary . for implementation details and other information, refer to the atmel qtouch library user guide - also available for download from atmel website. 8 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 7. avr cpu core 7.1 overview this section discusses the avr core architecture in gener al. the main function of the cpu core is to ensure cor- rect program execution. the cpu must therefore be abl e to access memories, perform calculations, control peripherals, and handle interrupts. figure 7-1. block diagram of the avr architecture in order to maximize performance and parallelism, the avr uses a harvard architecture ? with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipelining. while one instruction is being executed, the next instruct ion is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycl e. the program memory is in-system reprogrammable flash memory. the fast-access register file contains 32 x 8-bit gene ral purpose working registers with a single clock cycle access time. this allows singl e-cycle arithmetic logic unit (alu) operati on. in a typical alu operation, two oper- flash program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu status and control i/o lines eeprom data bus 8-bit data sram direct addressing indirect addressing interrupt unit spi unit watchdog timer analog comparator i/o module 2 i/o module1 i/o module n 9 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ands are output from the register file, the operation is ex ecuted, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-bit indi rect address register pointers for data space addressing ? enabling efficient address calculations. one of the these add ress pointers can also be used as an address pointer for look up tables in flash program memory. these added f unction registers are the 16-bit x-, y-, and z-register, described later in this section. the alu supports arithmetic and logic operations betwee n registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic operation, the status register is updated to reflect information about the result of the operation. program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. most avr instructions have a single 16-bit word format. every program memory address contains a 16- or 32-bit instruction. program flash memory space is divided in two sections, the boot program section and the application program section. both sections have dedicated lock bits for write and read/write protection. the spm instruction that writes into the application flash me mory section must reside in the boot program section. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram, and c onsequently the stack size is only limited by the total sram size and the usage of the sram. all user programs must initialize the sp in the reset routine (before sub- routines or interrupts are executed). the stack pointer (sp) is read/write accessible in the i/o space. the data sram can easily be accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control registers in the i/o space with an additional global interrupt enable bit in the status register. all interrupts have a separate interrupt vector in the interrupt vector table. the interrupts have priority in accordance with their interrupt vector position. the lower the interrupt vector address, the higher the priority. the i/o memory space contains 64 addresses for cpu peripheral functions as control registers, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the reg- ister file, 0x20 - 0x5f. in addition, the atmega48a/pa/88a/pa/168a/pa/328/p has extended i/o space from 0x60 - 0xff in sram where only the st/sts/std and ld/lds/ldd instructions can be used. 7.2 alu ? arithm etic logic unit the high-performance avr alu operates in direct connection with all the 32 general purpose working registers. within a single clock cycle, arithmetic operations betwee n general purpose registers or between a register and an immediate are executed. the alu operations are divided in to three main categories ? arithmetic, logical, and bit- functions. some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. see the ?instruction set? section for a detailed description. 7.3 status register the status register contains information about the result of the most recently executed arithmetic instruction. this information can be used for altering program flow in order to perform conditional operations. note that the status register is updated afte r all alu operations, as specif ied in the instruction set refe rence. this will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. this must be handled by software. 10 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 7.3.1 sreg ? avr status register the avr status register ? sreg ? is defined as: ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set for the interrup ts to be enabled. the individual interrupt enable control is then performed in separate control registers. if the glob al interrupt enable register is cleared, none of the inter- rupts are enabled independent of the individual interrupt enable settings. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. the i-bit can also be set and cleared by the application with the sei and cli instructions, as described in the instruction set reference. ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (bit st ore) use the t-bit as source or destination for the oper- ated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag h indicates a half carry in some arithmetic operations. ha lf carry is useful in bcd arithmetic. see the ?instruction set description? for detailed information. ? bit 4 ? s: sign bit, s = n ?? v the s-bit is always an exclusive or between the negative flag n and the two?s complement overflow flag v. see the ?instruction set description? for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v supports two?s complement arithmetic. see the ?instruction set descrip- tion? for detailed information. ? bit 2 ? n: negative flag the negative flag n indicates a negative result in an ar ithmetic or logic operation. see the ?instruction set description? for det ailed information. ? bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see the ?instruction set description? for detailed information. 7.4 general purpose register file the register file is optimized for the avr enhanced risc instruction set. in order to achieve the required perfor- mance and flexibility, the followin g input/output scheme s are supported by the register file: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? two 8-bit output operands and one 16-bit result input bit 76543210 0x3f (0x5f) i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 11 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? one 16-bit output operand and one 16-bit result input figure 7-2 shows the structure of the 32 general purpose working registers in the cpu. figure 7-2. avr cpu general purpose working registers most of the instructions operating on the register file have direct access to all registers, and most of them are sin- gle cycle instructions. as shown in figure 7-2 , each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. although not bei ng physically implemented as sram locations, this memory organization provides great flexibility in access of the registers, as the x-, y- and z-pointer registers can be set to index any register in the file. 7.4.1 the x-register, y-register, and z-register the registers r26...r31 have some added functions to their general purpose usage. these registers are 16-bit address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as described in figure 7-3 . figure 7-3. the x-, y-, and z-registers in the different addressing modes these address registers have functions as fixed displacement, automatic incre- ment, and automatic decrement (see the instruction set reference for details). 7 0 addr. r0 0x00 r1 0x01 r2 0x02 ? r13 0x0d general r14 0x0e purpose r15 0x0f working r16 0x10 registers r17 0x11 ? r26 0x1a x-register low byte r27 0x1b x-register high byte r28 0x1c y-register low byte r29 0x1d y-register high byte r30 0x1e z-register low byte r31 0x1f z-register high byte 15 xh xl 0 x-register 707 0 r27 (0x1b) r26 (0x1a) 15 yh yl 0 y-register 707 0 r29 (0x1d) r28 (0x1c) 15 zh zl 0 z-register 70 7 0 r31 (0x1f) r30 (0x1e) 12 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 7.5 stack pointer the stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. note that the stack is implemented as growing from higher to lower memory locations. the stack pointer register always points to the top of the stack. the stack pointer points to the data sram stack area where the subrouti ne and interrupt stacks ar e located. a stack push command will decrease the stack pointer. the stack in the data sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. initial stack pointer value equals the last address of the internal sram and the stack pointer must be set to point above start of the sram, see table 8-3 on page 18 . see table 7-1 for stack pointer details. the avr stack pointer is implemented as two 8-bit registers in the i/o space. the number of bits actually used is implementation dependent. note that the data space in some implementations of the avr architecture is so small that only spl is needed. in this case , the sph register will not be present. 7.5.1 sph and spl ? stack pointer high and stack pointer low register table 7-1. stack pointer instructions instruction stack pointer description push decremented by 1 data is pushed onto the stack call icall rcall decremented by 2 return address is pushed onto the stack with a subroutine call or interrupt pop incremented by 1 data is popped from the stack ret reti incremented by 2 return address is popped from the stack with return from subroutine or return from interrupt bit 151413121110 9 8 0x3e (0x5e) sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph 0x3d (0x5d) sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value ramend ramend rame nd ramend ramend ramend ramend ramend ramend ramend rame nd ramend ramend ramend ramend ramend 13 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 7.6 instruction execution timing this section describes the general access timing concepts for instruction execution. the avr cpu is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal clock division is used. figure 7-4 shows the parallel instruction fetches and instruct ion executions enabled by the harvard architecture and the fast-access register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz with the correspondin g unique results for functions per cost, functions per clocks, and functions per power-unit. figure 7-4. the parallel instruction fetches and instruction executions figure 7-5 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destination register. figure 7-5. single cycle alu operation 7.7 reset and inte rrupt handling the avr provides several different interrupt sources. these interrupts and the separate reset vector each have a separate program vector in the program memory space. all interrupts are assigned individual enable bits which must be written logic one together with the global interrupt enable bit in the status register in order to enable the interrupt. depending on the program counter value, interr upts may be automatically disabled when boot lock bits blb02 or blb12 are programmed. this feature improves software security. see the section ?memory program- ming? on page 285 for details. the lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. the complete list of vectors is shown in ?interrupts? on page 57 . the list also determines the priority levels of the different interrupts. the lower the address the hi gher is the priority level. reset has the highest priority, and next is int0 ? the external interrupt request 0. the interrupt vectors can be moved to the start of the boot flash sec- tion by setting the ivsel bit in the mcu control register (mcucr). refer to ?interrupts? on page 57 for more information. the reset vector can also be moved to the start of the boot flash section by programming the bootrst fuse, see ?boot loader support ? read-while-write self-programming? on page 269 . clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 cpu total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 clk cpu 14 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 when an interrupt occurs, the global interrupt enable i-bit is cleared and all interrupts are disabled. the user soft- ware can write logic one to the i-bit to enable nested interrupts. all enabled interrupts can then interrupt the current interrupt routine. the i-bit is automatically set when a return from interrupt instruction ? reti ? is executed. there are basically two types of interrupts. the first type is triggered by an event that sets the interrupt flag. for these interrupts, the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, and hardware clears the corresponding inte rrupt flag. interrupt flags can also be cleared by writ- ing a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be se t and remembered un til the interrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by order of priority. the second type of interrupts will trigger as long as the interrupt condition is present. these inte rrupts do not nec- essarily have interrupt flags. if the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. when the avr exits from an inte rrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. note that the status register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. this must be handled by software. when using the cli instruction to dis able interrupts, the interrupts will be im mediately disabled. no interrupt will be executed after the cli instruction, even if it occurs simu ltaneously with the cli instruction. the following example shows how this can be used to avoid interr upts during the tim ed eeprom write sequence. when using the sei instruction to enabl e interrupts, the instruct ion following sei will be ex ecuted before any pend- ing interrupts, as shown in this example. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eempe ; start eeprom write sbi eecr, eepe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ _cli(); eecr |= (1< 16 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 8. avr memories 8.1 overview this section describes the different memories in the atmega48a/pa/88a/pa/168a/pa/328/p. the avr architec- ture has two main memory spaces, the data memory and the program memory space. in addition, the atmega48a/pa/88a/pa/168a/pa/ 328/p features an eeprom memory for data storag e. all three memory spaces are linear and regular. 8.2 in-system reprogrammable flash program memory the atmega48a/pa/88a/pa/168a/pa/328/p contains 4/8/16/32kbytes on-chip in-system reprogrammable flash memory for program storage. since all avr instructi ons are 16 or 32 bits wide, the flash is organized as 2/4/8/16k x 16. for software security, the flash program memory space is divided into two sections, boot loader section and application program section in atmega88pa and atmega168pa. see spmen description in section ?spmcsr ? store program memory control and status register? on page 283 for more details. the flash memory has an en durance of at least 10,000 write/erase cycles. the atmega48a/pa/88a/pa/168a/pa/328/p program counter (pc) is 11/12/13/14 bits wide, thus addressing the 2/4/8/16k program memory locations. the operation of b oot program section and associated boot lock bits for software protection are described in detail in ?self-programming the flash, atmega 48a/48pa? on page 261 and ?boot loader support ? read-while-write self-programming? on page 269 . ?memory programming? on page 285 contains a detailed description on flash programming in spi- or parallel programming mode. constant tables can be allocated within the entire pr ogram memory address space (see the lpm ? load program memory instruction description). timing diagrams for instruction fetc h and execution are presented in ?instruction execution timing? on page 13 . 17 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 8-1. program memory map atmega 48a/48pa figure 8-2. program memory map atmega88a, atmega88pa, atmega168a, atmega168pa, atmega328 and atmega328p 0x0000 0x7ff program memory application flash section 0x0000 0x0fff/0x1fff/0x3fff program memory application flash section boot flash section 18 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 8.3 sram data memory figure 8-3 shows how the atmega48a/ pa/88a/pa/168a/pa/32 8/p sram memory is organized. the atmega48a/pa/88a/pa/168a/pa/328/p is a complex microc ontroller with more peripheral units than can be supported within the 64 locations reserved in the opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/s ts/std and ld/lds/ldd instructions can be used. the lower 768/1280/1280/2303 data memory locations address both the register file, the i/o memory, extended i/o memory, and the internal data sram. the first 32 locations address the register file, the next 64 location the standard i/o memory, then 160 locations of extended i/o memory, and the next 512/1024/1024/2048 locations address the internal data sram. the five different addressing modes for the data memory co ver: direct, indirect with displacement, indirect, indi- rect with pre-decrement, and indirect with post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space. the indirect with displacement mode reaches 63 address lo cations from the base address given by the y- or z- register. when using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers x, y, and z are decremented or incremented. the 32 general purpose working registers, 64 i/o registers, 160 extended i/o registers, and the 512/1024/1024/2048 bytes of internal data sram in t he atmega48a/pa/88a/pa/168a/pa/328/p are all accessi- ble through all these addressing modes. the register file is described in ?general purpose register file? on page 10 . figure 8-3. data memory map 32 registers 64 i/o registers internal sram (512/1024/1024/204 8 x 8 ) 0x0000 - 0x001f 0x0020 - 0x005f 0x02ff/0x04ff/0x4ff/0x0 8 ff 0x0060 - 0x00ff data memory 160 ext i/o reg. 0x0100 19 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 8.3.1 data memory access times this section describes the general access timing concept s for internal memory access. the internal data sram access is performed in two clk cpu cycles as described in figure 8-4 . figure 8-4. on-chip data sram access cycles 8.4 eeprom data memory the atmega48a/pa/88a/pa/168a/pa/328/ p contains 256/512 /512/1kbytes of data eepr om memory. it is orga- nized as a separate data space, in which single bytes can be read and written. the eeprom has an endurance of at least 100,000 write/ erase cycles. the access betw een the eeprom and the cpu is described in the following, specifying the eeprom addres s registers, the eeprom data regist er, and the eeprom control register. ?memory programming? on page 285 contains a detailed description on eeprom programming in spi or parallel programming mode. 8.4.1 eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access time for the eeprom is given in table 8-2 . a self-timing function, however, lets the user software detect when the next byte can be writ ten. if the user code c ontains instructions that write the eeprom, some pre- cautions must be taken. in heavily filtered power supplies, v cc is likely to rise or fall slowly on power-up/down. this causes the device for some period of time to run at a voltage lower than specified as minimum for the clock fre- quency used. see ?preventing eeprom corruption? on page 20 for details on how to avoid problems in these situations. in order to prevent unintentional eeprom writes, a specific write procedure must be followed. refer to the description of the eepr om control register for details on this. when the eeprom is read, the cpu is halted for four cloc k cycles before the next instruction is executed. when the eeprom is written, the cpu is halted for two clock cycles before the next instruction is executed. clk wr rd data data address address valid t1 t2 t3 compute address read write cpu memory access instruction next instruction 20 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 8.4.2 preventing eeprom corruption during periods of low v cc, the eeprom data can be corrup ted because the supply volt age is too low for the cpu and the eeprom to operate properly. these issues are the same as for board level systems using eeprom, and the same design solutions should be applied. an eeprom data corruption can be caused by two situatio ns when the voltage is too low. first, a regular write sequence to the eeprom requires a mini mum voltage to operate co rrectly. second ly, the cpu itself can execute instructions incorrectly, if the supply voltage is too low. eeprom data corruption can easily be avoi ded by following this design recommendation: keep the avr reset active (low) dur ing periods of insufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod). if the detection level of the internal bod does not match the needed detection level, an external low v cc reset protection circuit can be used. if a reset occurs while a write operation is in progress, the write operation will be comple ted provided that the power supply voltage is sufficient. 8.5 i/o memory the i/o space definition of the atmega48a/pa/88a/pa/168a/pa/328/p is shown in ?register summary? on page 622 . all atmega48a/pa/88a/pa/168a/pa/328/p i/os and peripherals are placed in the i/o space. all i/o locations may be accessed by the ld/lds/ldd and st/sts/std instructions, transferring data between the 32 general purpose working registers and the i/o space. i/o registers within th e address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. refer to the instruction set section for more details. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be us ed. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addr esses. the atmega48a/pa/88a/pa/168a/pa/328/p is a complex microcontroller with more peripheral units th an can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresses should never be written. some of the status flags are cleared by writing a logical one to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specif ied bit, and can therefore be used on registers containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. the i/o and peripherals control registers are explained in later sections. 8.5.1 general purpose i/o registers the atmega48a/pa/88a/pa/168a/pa/328/p contains three general purpose i/o registers. these registers can be used for storing any information, and they are particula rly useful for storing global variables and status flags. general purpose i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi, cbi, sbis, and sbic instructions. 21 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 8.6 register description 8.6.1 eearh and eearl ? the eeprom address register ? bits [15:10] ? reserved these bits are reserved bits in the atmega48a/pa/88a/pa/168a/pa/32 8/p and will always read as zero. ? bits 9:0 ? eear[9: 0]: eeprom address the eeprom address registers ? eea rh and eearl specify the eeprom addr ess in the 256/ 512/512/1kbytes eeprom space. the eeprom data bytes are addres sed linearly between 0 and 255/511/511/1023. the initial value of eear is undefined. a pr oper value must be written be fore the eeprom may be accessed. note: 1. eear9 and eear8 are unused bits in atmega 48a/48pa and must always be written to zero. 8.6.2 eedr ? the eeprom data register ? bits 7:0 ? eedr[7:0]: eeprom data for the eeprom write operation, the eedr register cont ains the data to be written to the eeprom in the address given by the eear register. for the eeprom read operation, the ee dr contains the data read out from the eeprom at the address given by eear. 8.6.3 eecr ? the eeprom control register ? bits 7:6 ? reserved these bits are reserved bits in the atmega48a/pa/88a/pa/168a/pa/32 8/p and will always read as zero. ? bits 5, 4 ? eepm1 and eepm0: eeprom programming mode bits the eeprom programming mode bit setting defines which pr ogramming action that will be triggered when writing eepe. it is possible to program data in one atomic operati on (erase the old value and program the new value) or to split the erase and write operations in two different operations. the programming times for the different modes are shown in table 8-1 . while eepe is set, any write to eepmn will be ignored. during reset, the eepmn bits will be reset to 0b00 unless the eepr om is busy programming. bit 151413121110 9 8 0x22 (0x42) ??????eear9 (1) eear8 (1) eearh 0x21 (0x41) eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl 76543210 read/write rrrrrrrr/w r/w r/w r/w r/w r/w r/w r/w r/w initial value0000000x xxxxxxxx bit 76543210 0x20 (0x40) msb lsb eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 765432 10 0x1f (0x3f) ? ? eepm1 eepm0 eerie eempe eepe eere eecr read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 x x 0 0 x 0 22 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bit 3 ? eerie: eeprom ready interrupt enable writing eerie to one enables the eeprom ready interrupt if the i bit in sreg is set. writing eerie to zero dis- ables the interrupt. the eeprom ready interrupt generat es a constant interrupt when eepe is cleared. the interrupt will not be generat ed during eeprom write or spm. ? bit 2 ? eempe: eeprom master write enable the eempe bit determines whether setti ng eepe to one causes the eeprom to be written. when eempe is set, setting eepe within four clock cycles will write data to the eeprom at the se lected address if eempe is zero, set- ting eepe will have no effect. when eempe has been writt en to one by software, hardw are clears the bit to zero after four clock cyc les. see the description of the eepe bit for an eeprom write procedure. ? bit 1 ? eepe: eeprom write enable the eeprom write enable signal eepe is the write stro be to the eeprom. when addr ess and data are correctly set up, the eepe bit must be written to one to write the value in to the eeprom. the eempe bit must be written to one before a logical one is writte n to eepe, otherwise no eeprom write takes place. the following procedure should be followed when writi ng the eeprom (the order of steps 3 and 4 is not essential): 1. wait until eepe becomes zero. 2. wait until spmen in spmcsr becomes zero. 3. write new eeprom address to eear (optional). 4. write new eeprom data to eedr (optional). 5. write a logical one to the eempe bit while writing a zero to eepe in eecr. 6. within four clock cycles after sett ing eempe, write a logical one to eepe. the eeprom can not be programmed during a cpu write to the flash memory. the software must check that the flash programming is co mpleted before initiating a new eeprom write. st ep 2 is only relevant if the software con- tains a boot loader allowing the cpu to program the flash. if the flash is never being updated by the cpu, step 2 can be omitted. see ?boot loader support ? read-while-write self-programming? on page 269 for details about boot programming. caution: an interrupt between step 5 and st ep 6 will make the write cycle fa il, since the eeprom master write enable will time-out. if an interrupt r outine accessing the eeprom is inte rrupting another eeprom access, the eear or eedr register will be modified , causing the interrupted eeprom acce ss to fail. it is recommended to have the global interrupt flag cleared during all the steps to avoid these problems. when the write acce ss time has elapsed, the eepe bit is cleared by hardware. the user soft ware can poll this bit and wait for a zero before writing the next byte. when eepe has been set, the cpu is halted for two cycles before the next instruction is executed. table 8-1. eeprom mode bits eepm1 eepm0 programming time operation 0 0 3.4ms erase and write in one operation (atomic operation) 0 1 1.8ms erase only 1 0 1.8ms write only 1 1 ? reserved for future use 23 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bit 0 ? eere: eeprom read enable the eeprom read enable signal eere is the read strobe to the eeprom. when the correct address is set up in the eear register, the eere bit must be written to a logic one to trigger the eepr om read. the eeprom read access takes one instruction, and the requested data is available immediately. when the eeprom is read, the cpu is halted for four cycles before the next instruction is executed. the user should poll the eepe bit before st arting the read o peration. if a write operation is in progress, it is neither possible to read the eeprom, nor to change the eear register. the calibrated oscillator is used to time the eeprom accesses. table 8-2 lists the typical programming time for eeprom access from the cpu. the following code examples show one assembly and one c function for writing to the eeprom. the examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. the examples also assume that no flash boot loader is present in the software. if such code is present, th e eeprom write function must also wait for any ongoing spm command to finish. table 8-2. eeprom programming time symbol number of calibrated rc osci llator cycles typ programming time eeprom write (from cpu) 26,368 3.3ms 24 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 assembly code example eeprom_write: ; wait for completion of previous write sbic eecr,eepe rjmp eeprom_write ; set up address (r18:r17) in address register out eearh, r18 out eearl, r17 ; write data (r16) to data register out eedr,r16 ; write logical one to eempe sbi eecr,eempe ; start eeprom write by setting eepe sbi eecr,eepe ret c code example void eeprom_write( unsigned int uiaddress, unsigned char ucdata) { /* wait for completion of previous write */ while(eecr & (1< 27 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 9.1.4 asynchronous timer clock ? clk asy the asynchronous timer clock allows the asynchronous timer/counter to be clocked directly from an external clock or an external 32khz clock crystal. the dedicated clock domain allows using this timer/counter as a real- time counter even when the device is in sleep mode. 9.1.5 adc clock ? clk adc the adc is provided with a dedicated clock domain. this a llows halting the cpu and i/o clocks in order to reduce noise generated by digital circuitry. this gives more accurate adc conversion results. 9.2 clock sources the device has the following clock sour ce options, selectable by flash fuse bits as shown below. the clock from the selected source is input to the avr clock generator, and routed to the appropriate modules. note: 1. for all fuses ?1? means unprogrammed while ?0? means programmed. 9.2.1 default clock source the device is shipped with internal rc oscillator at 8. 0mhz and with the fuse ckdiv8 programmed, resulting in 1.0mhz system clock. the st artup time is set to maximum and time-o ut period enabled. (cksel = "0010", sut = "10", ckdiv8 = "0"). the default setting ensures that all users can make their desir ed clock source setting using any available programming interface. 9.2.2 clock startup sequence any clock source needs a sufficient v cc to start oscillating and a minimum num ber of oscillating cycles before it can be considered stable. to ensure sufficient v cc , the device issues an internal reset with a time-out delay (t tout ) after the device reset is released by all other reset sources. ?system control and reset? on page 46 describes the start conditions for the internal reset. the delay (t tout ) is timed from the watchdog oscillator and the number of cycles in the delay is set by the sutx and ckselx fuse bits. t he selectable delays are shown in table 9-2 . the frequency of the watchdog oscillator is voltage dependent as shown in ?typical characteristics ? (ta = -40c to 85c)? on page 324 . main purpose of the delay is to keep the avr in reset until it is supplied with minimum v cc . the delay will not mon- itor the actual voltag e and it will be required to sele ct a delay longer than the v cc rise time. if this is not possible, an table 9-1. device clocking options select (1) device clocking option cksel3...0 low power crystal oscillator 1111 - 1000 full swing crystal oscillator 0111 - 0110 low frequency crystal oscillator 0101 - 0100 internal 128khz rc oscillator 0011 calibrated internal rc oscillator 0010 external clock 0000 reserved 0001 table 9-2. number of watchdog oscillator cycles typ time-out (v cc = 5.0v) typ time-out (v cc = 3.0v) number of cycles 0ms 0ms 0 4.1ms 4.3ms 512 65ms 69ms 8k (8,192) 28 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 internal or external brown-out de tection circuit should be used. a bod circuit will ensure sufficient v cc before it releases the reset, and the time-out delay can be disabled. disabling the time-out delay withou t utilizing a brown- out detection circuit is not recommended. the oscillator is required to oscillate for a minimum numb er of cycles before the clock is considered stable. an internal ripple counter monito rs the oscillator output clock, and keeps the internal reset active for a given number of clock cycles. the reset is then releas ed and the device will start to execut e. the recommended oscillator start-up time is dependent on the cloc k type, and varies from 6 cycles for an exte rnally applied clock to 32k cycles for a low frequency crystal. the start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. when starting up from power-save or power-down mode, v cc is assumed to be at a sufficient level and only the start-up time is included. 9.3 low power crystal oscillator pins xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 9-2 on page 28 . either a quartz crystal or a ceramic resonator may be used. this crystal oscillator is a low power oscillator, with reduced voltage swing on the xtal2 output. it gives the low- est power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments. in these cases, refer to the ?full swing crystal os cillator? on page 29 . c1 and c2 should always be equal for both crystals and resonators. the optimal value of the capacitors depends on the crystal or resonator in use, the amount of stra y capacitance, and the electromagnetic noise of the environ- ment. some initial guidelines for choosing c apacitors for use with crystals are given in table 9-3 on page 28 . for ceramic resonators, the capacitor values given by the manufacturer should be used. figure 9-2. crystal oscillator connections the low power oscillator can operate in three different modes, each optimiz ed for a specific frequency range. the operating mode is se lected by the fuses cksel3...1 as shown in table 9-3 on page 28 . table 9-3. low power crystal osc illator oper ating modes (3) frequency range (mhz) recommended range for capacitors c1 and c2 (pf) cksel3...1 (1) 0.4 - 0.9 ? 100 (2) 0.9 - 3.0 12 - 22 101 3.0 - 8.0 12 - 22 110 8.0 - 16.0 12 - 22 111 xtal2 (tosc2) xtal1 (tosc1) gnd c2 c1 29 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 notes: 1. this is the recommended cksel sett ings for the difference frequency ranges. 2. this option should not be used with cr ystals, only with ceramic resonators. 3. if the crystal frequency exceeds the spec ification of the device (depends on v cc ), the ckdiv8 fuse can be pro- grammed in order to divide the internal frequency by 8. it must be ensured that the resulting divided clock meets the frequency specification of the device. the cksel0 fuse together with the sut1...0 fuses select th e start-up time s as shown in table 9-4 . notes: 1. these options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the app lication. these options are not suitable for crystals. 2. these options are intended for use with ceramic resonators and will ensure frequency stability at start-up. they can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency sta- bility at start-up is not im portant for the application. 9.4 full swing crystal oscillator pins xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 9-2 on page 28 . either a quartz crystal or a ceramic resonator may be used. this crystal oscillator is a full swing o scillator, with rail-to-rail swing on the xtal 2 output. this is useful for driving other clock inputs and in noisy environments. the current consumption is higher than the ?low power crystal oscillator? on page 28 . note that the full swing crystal oscillator will onl y operate for v cc = 2.7 - 5.5 volts. c1 and c2 should always be equal for both crystals and resonators. the optimal value of the capacitors depends on the crystal or resonator in use, the amount of stra y capacitance, and the electromagnetic noise of the environ- ment. some initial guidelines for choosing c apacitors for use with crystals are given in table 9-6 on page 30 . for ceramic resonators, the capacitor values given by the manufacturer should be used. table 9-4. start-up times for the low power crystal osc illator clock selection oscillator source / power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) cksel0 sut1...0 ceramic resonator, fast rising power 258 ck 14ck + 4.1ms (1) 000 ceramic resonator, slowly rising power 258 ck 14ck + 65ms (1) 001 ceramic resonator, bod enabled 1k ck 14ck (2) 010 ceramic resonator, fast rising power 1k ck 14ck + 4.1ms (2) 011 ceramic resonator, slowly rising power 1k ck 14ck + 65ms (2) 100 crystal oscillator, bod enabled 16k ck 14ck 1 01 crystal oscillator, fast rising power 16k ck 14ck + 4.1ms 1 10 crystal oscillator, slowly rising power 16k ck 14ck + 65ms 1 11 30 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 the operating mode is selected by the fuses cksel3...1 as shown in table 9-5 . notes: 1. if the cryatal frequency exceeds the s pecification of the device (depends on v cc ), the ckdiv8 fuse can be pro- grammed in order to divide the internal frequency by 8. it must be ensured that the resulting divided clock meets the frequency specification of the device. figure 9-3. crystal oscillator connections notes: 1. these options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the app lication. these options are not suitable for crystals. 2. these options are intended for use with ceramic resonators and will ensure frequency stability at start-up. they can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency sta- bility at start-up is not im portant for the application. table 9-5. full swing crystal osc illator operating modes frequency range (1) (mhz) recommended range for capacitors c1 and c2 (pf) cksel3...1 0.4 - 20 12 - 22 011 table 9-6. start-up times for the full swing crystal oscillato r clock selection oscillator source / power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) cksel0 sut1...0 ceramic resonator, fast rising power 258 ck 14ck + 4.1ms (1) 000 ceramic resonator, slowly rising power 258 ck 14ck + 65ms (1) 001 ceramic resonator, bod enabled 1k ck 14ck (2) 010 ceramic resonator, fast rising power 1k ck 14ck + 4.1ms (2) 011 ceramic resonator, slowly rising power 1k ck 14ck + 65ms (2) 100 crystal oscillator, bod enabled 16k ck 14ck 1 01 crystal oscillator, fast rising power 16k ck 14ck + 4.1ms 1 10 crystal oscillator, slowly rising power 16k ck 14ck + 65ms 1 11 xtal2 (tosc2) xtal1 (tosc1) gnd c2 c1 31 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 9.5 low frequency crystal oscillator the low-frequency crystal oscillator is optimized for use with a 32.768khz wa tch crystal. when se lecting crystals, load capacitance and crystal?s equivalent series resistance, esr must be taken into consideration. both values are specified by the crystal vendor. atmega48a/pa/88a/pa/168a/pa/328/p oscillator is optimized for very low power consumption, and thus when selecting crystals, see table for maximum esr recommendations on 6.5pf, 9.0pf and 12.5pf crystals note: 1. maximum esr is typical value based on characterization the low-frequency crystal os cillator provides an inter nal load capacitance, see table 9-8 at each tosc pin. the capacitance (ce+ci) needed at each tosc pin can be calculated by using: where: ? ce - is optional external capacitors as described in figure 9-2 on page 28 ? ci - is the pin capacitance in table 9-8 ? cl - is the load capacitance for a 32.768khz crystal specified by the crystal vendor ? cs - is the total stray capacitance for one tosc pin. crystals specifying load capacitance (cl) higher than 6 pf, require external capacitors applied as described in fig- ure 9-2 on page 28 . the low-frequency crystal osc illator must be selected by setting the cksel fuses to ?0 110? or ?0111?, as shown in table 9-10 on page 32 . start-up times are determined by the sut fuses as shown in table 9-9 . table 9-7. maximum esr recommendation for 32.768khz crystal crystal cl (pf) max esr [k ? ] (1) 6.5 75 9.0 65 12.5 30 table 9-8. capacitance for low- frequency oscillator device 32khz osc. type cap(xtal1/tosc1) cap(xtal2/tosc2) atmega48a/pa/88a/pa/168a/pa/3 28/p system osc. 18pf 8pf timer osc. 18pf 8pf table 9-9. start-up times for the lo w-frequency crystal os cillator clock selection sut1...0 additional delay from reset (v cc = 5.0v) recommended usage 00 4 ck fast rising power or bod enabled 01 4 ck + 4.1ms slowly rising power 10 4 ck + 65ms stable frequency at start-up 11 reserved c 2 cl ? c s ? = 32 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. this option should only be used if frequency stabilit y at start-up is not important for the application 9.6 calibrated internal rc oscillator by default, the internal rc oscillato r provides an approximate 8.0mhz cl ock. though voltag e and temperature dependent, this clock can be very accurately calibrated by the user. see table 29-14 on page 311 for more details. the device is shipped with the ckdiv8 fuse programmed. see ?system clock prescaler? on page 34 for more details. this clock may be selected as the system cloc k by programming the cksel fuses as shown in table 9-11 . if selected, it will operate with no external components. during reset, hardware load s the pre-program med calibration value into the osccal register and th ereby automatically calibra tes the rc oscillator. the accuracy of this cali- bration is shown as factory calibration in table 29-14 on page 311 . by changing the osccal register from sw, see ?osccal ? oscillator calibra tion register? on page 36 , it is pos- sible to get a higher calibration accuracy than by using the factory calibration. the accuracy of this calibration is shown as user calibration in table 29-14 on page 311 . when this oscillator is used as the chip clock, the watchdog oscillator will still be used for the watchdog timer and for the reset time-out. for more information on the pre-programmed calibration value, see the section ?cali- bration byte? on page 289 . notes: 1. the device is shipped with this option selected. 2. if 8mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse can be pro- grammed in order to divide the internal frequency by 8. when this oscillator is selected , start-up times are de termined by the sut fuses as shown in table 9-12 . note: 1. if the rstdisbl fuse is programmed, this start-up time will be increased to 14ck + 4.1ms to ensure programming mode can be entered. 2. the device is shipped wit h this option selected. table 9-10. start-up times for the lo w-frequency crystal os cillator clock selection cksel3... 0 start-up time from power-down and power-save recommended usage 0100 (1) 1k ck 0101 32k ck stable frequency at start-up table 9-11. internal calibrated rc o scillator operating modes frequency range (2) (mhz) cksel3...0 7.3 - 8.1 0010 (1) table 9-12. start-up times for the internal calib rated rc oscillator clock selection power conditions start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) sut1...0 bod enabled 6 ck 14ck (1) 00 fast rising power 6 ck 14ck + 4.1ms 01 slowly rising power 6 ck 14ck + 65ms (2) 10 reserved 11 33 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 9.7 128khz internal oscillator the 128khz internal os cillator is a low power oscillator providing a clock of 128khz. t he frequency is nominal at 3v and 25 ? c. this clock may be select as the system clock by programming the cksel fuses to ?11? as shown in table 9-13 . note: 1. note that the 128khz oscillator is a very low power clock source, and is not designed for high accuracy. when this clock source is selected, start-up times are determined by the sut fuses as shown in table 9-14 . note: 1. if the rstdisbl fuse is programmed, this start-up time will be increased to 14ck + 4.1ms to ensure programming mode can be entered. 9.8 external clock to drive the device from an external cloc k source, xtal1 should be driven as shown in figure 9-4 . to run the device on an external cloc k, the cksel fuses must be pr ogrammed to ?0000? (see table 9-15 ). figure 9-4. external clock drive configuration when this clock source is selected, start-up times are determined by the sut fuses as shown in table 9-16 . table 9-13. 128khz internal oscillator operating modes nominal frequency (1) cksel3...0 128khz 0011 table 9-14. start-up times for the 128khz internal oscillator power conditions start-up time from power- down and power-save additional delay from reset sut1...0 bod enabled 6 ck 14ck (1) 00 fast rising power 6 ck 14ck + 4ms 01 slowly rising power 6 ck 14ck + 64ms 10 reserved 11 table 9-15. crystal oscillator clock frequency frequency cksel3...0 0 - 20mhz 0000 pb7 external clock s ignal xtal2 xtal1 gnd 34 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 when applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the mcu. a variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. if changes of more than 2% is required, ensure that the mcu is kept in reset during the changes. note that the system clock prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stabl e operation. refer to ?system clock prescaler? on page 34 for details. 9.9 clock output buffer the device can output the system clock on the clko pi n. to enable the output, the ckout fuse has to be pro- grammed. this mode is suitable when the chip clock is us ed to drive other circuits on the system. the clock also will be output during reset, and the nor mal operation of i/o pin will be overri dden when the fuse is programmed. any clock source, including the internal rc oscillator, c an be selected when the clock is output on clko. if the system clock prescaler is used, it is the divided system clock that is output. 9.10 timer/counter oscillator atmega48a/pa/88a/pa/168a/pa/328/p uses the same cr ystal oscillator for low-frequency oscillator and timer/counter oscillator. see ?low frequency crystal oscillator? on page 31 for details on the oscillator and crys- tal requirements. atmega48a/pa/88a/pa/168a/pa/328/p share the timer/c ounter oscillator pins (tosc1 and tosc2) with xtal1 and xtal2. when using the time r/counter oscillator, the system clock needs to be four times the oscilla- tor frequency. due to this and the pin sharing, the timer/counte r oscillator can only be used when the calibrated internal rc oscillator is sele cted as system clock source. applying an external clock source to tosc1 can be done if extclk in the assr register is written to logic one. see ?asynchronous operation of timer/counter2? on page 153 for further description on selecting external clock as input instead of a 32.768khz watch crystal. 9.11 system clock prescaler the atmega48a/pa/88a/pa/168a/pa/328/p has a system clock prescaler, and the system clock can be divided by setting the ?clkpr ? clock prescale register? on page 36 7. this feature can be used to decrease the system clock frequency and the power consumption when the requir ement for processing power is low. this can be used with all clock source option s, and it will affect the cl ock frequency of the cpu and all synchr onous peripherals. clk i/o , clk adc , clk cpu , and clk flash are divided by a factor as shown in table 29-16 on page 312 . when switching between prescaler settings, the system clock prescaler ensures that no glitches occurs in the clock system. it also ensures that no intermediate frequency is higher than neither the clock frequency correspond- ing to the previous setting, nor the clock frequency corresponding to the new setting. the ripple counter that implements the prescaler runs at the frequency of the u ndivided clock, which may be faster than the cpu's clock frequency. hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to the ot her cannot be exactly predicted. from the time the clkps table 9-16. start-up times for the external clock selection power conditions start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) sut1...0 bod enabled 6 ck 14ck 00 fast rising power 6 ck 14ck + 4.1ms 01 slowly rising power 6 ck 14ck + 65ms 10 reserved 11 35 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 values are written, it takes between t1 + t2 and t1 + 2 * t2 before the new clock frequency is active. in this inter- val, 2 active clock edges are produced. here, t1 is the pr evious clock period, and t2 is the period corresponding to the new prescaler setting. to avoid unintentional changes of clock frequency, a special write procedure must be followed to change the clkps bits: 1. write the clock prescaler change enable (clkpce) bit to one and all other bits in clkpr to zero. 2. within four cycles, write the desired valu e to clkps while writing a zero to clkpce. interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. 36 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 9.12 register description 9.12.1 osccal ? oscillato r calibration register ? bits 7:0 ? cal[7:0]: oscillator calibration value the oscillator calibration register is used to trim the calibrated internal rc oscillator to remove process varia- tions from the oscillator frequency. a pre-programmed calibration value is automatically written to this register during chip reset, giving the factory calibrated frequency as specified in table 29-14 on page 311 . the application software can write this register to change the oscillato r frequency. the oscillator can be calibrated to frequencies as specified in table 29-14 on page 311 . calibration outside that range is not guaranteed. note that this oscillator is used to time eeprom and flash write accesses, and these write ti mes will be affected accordingly. if the eeprom or flash are written, do not calibrate to more than 8.8mhz. otherwise, the eeprom or flash write may fail. the cal7 bit determines the range of op eration for the oscillator. setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. the two frequency ranges are overlapping, in other words a setting of osccal = 0x7f gives a higher frequency than osccal = 0x80. the cal6...0 bits are used to tune the frequency within the selected range. a setting of 0x00 gives the lowest fre- quency in that range, and a setting of 0x7f gives the highest frequency in the range. 9.12.2 clkpr ? clock prescale register ? bit 7 ? clkpce: clock prescaler change enable the clkpce bit must be written to l ogic one to enable change of the clkps bits. th e clkpce bit is only updated when the other bits in clkpr are simultaneously written to zero. clkpce is cleared by hardware four cycles after it is written or when clkps bits are written. rewriti ng the clkpce bit within this time-out period does neither extend the time-out period, nor clear the clkpce bit. ? bits 3:0 ? clkps[3:0]: clock prescaler select bits 3 - 0 these bits define the division factor between the selected clock source and the internal system clock. these bits can be written run-time to vary the clock frequency to suit the application requirements. as the divider divides the master clock input to the mcu, the speed of all synchro nous peripherals is reduced when a division factor is used. the division factors are given in table 9-17 on page 37 . the ckdiv8 fuse determines the initial value of the clkps bits. if ckdiv8 is unprogrammed, t he clkps bits will be reset to ?0000?. if ckdiv8 is programmed, clkps bits are reset to ?0011?, giving a division factor of 8 at start up. this feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. note that any value can be written to the clkps bits regardless of the ckdiv8 fuse setting. the application software must ensure that a sufficient divi sion factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. the device is shipped with the ckdiv8 fuse programmed. bit 76543210 (0x66) cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value device specific calibration value bit 76543210 (0x61) clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 clkpr read/write r/w r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description 37 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 table 9-17. clock prescaler select clkps3 clkps2 clkps1 clkps0 clock division factor 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved 38 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 10. power management and sleep modes sleep modes enable the application to shut down unused modules in the mcu, thereby saving power. the avr provides various sleep modes allowing the user to tailor the power consumption to the application?s requirements. when enabled, the brown-out detector (bod) actively moni tors the power supply voltage during the sleep periods. to further save power, it is possible to disable the bod in some sleep modes. see ?bod disable (1) ? on page 39 for more details. 10.1 sleep modes figure 9-1 on page 26 presents the different clock systems in the atmega48a/pa/88a/pa/168a/pa/328/p, and their distribution. the figure is helpful in selecting an appropriate sleep mode. table 10-1 shows the different sleep modes, their wake up sources bod disable ability. (1) note: 1. bod disable is only available for atmega48pa/88pa/168pa/328p. notes: 1. only recommended with external crystal or resonator selected as clock source. 2. if timer/counter2 is running in asynchronous mode. 3. for int1 and int0, only level interrupt. to enter any of the six sle ep modes, the se bit in smcr must be wri tten to logic one and a sleep instruction must be executed. the sm2, sm1, and sm0 bits in the smcr register select which sleep mode (idle, adc noise reduction, power-down, power-save, standby, or extended standby) will be activated by the sleep instruction. see table 10-2 on page 43 for a summary. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu wakes up. the mcu is then halted for four cycles in addition to the start- up time, executes the interrupt routine, and resumes execution from the instruc- tion following sleep. the contents of the register file and sram are unaltered when the device wakes up from sleep. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. table 10-1. active clock domains and wake-up sour ces in the different sleep modes. active clock domains osc illators wake-up sources software bod disable sleep mode clk cpu clk flash clk io clk adc clk asy main clock source enabled timer oscillator enabled int1, int0 and pin change twi address match timer2 spm/eeprom ready adc wdt other i/o idle xxx x x (2) x x x x xxx adc noise reduction xx x x (2) x (3) xx (2) xxx power-down x (3) xxx power-save x x (2) x (3) xx x x standby (1) xx (3) xxx extended standby x (2) xx (2) x (3) xx x x 39 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 10.2 bod disable (1) when the brown-out detector (bod) is enabled by bodlevel fuses - see table 28-7 on page 287 and onwards, the bod is actively monitoring the power supply voltage durin g a sleep period. to save power, it is possible to dis- able the bod by software for some of the sleep modes, see table 10-1 on page 38 . the sleep mode power consumption will then be at the same level as when bod is globally disabled by fuses. if bod is disabled in soft- ware, the bod function is turned off immediately after en tering the sleep mode. upon wake-up from sleep, bod is automatically enabled again. this ensures safe operation in case the v cc level has dropped during the sleep period. when the bod has been disabled, the wake-up time from sleep mode will be approximately 60 s to ensure that the bod is working correctly before the mcu continues executing code. bod disable is controlled by bit 6, bods (bod sleep) in the contro l register mcucr, see ?mcucr ? mcu con- trol register? on page 44 . writing this bit to one turns off the bod in re levant sleep modes, while a zero in this bit keeps bod active. default setting keeps bod active, i.e. bods set to zero. writing to the bods bit is controlled by a timed sequence and an enable bit, see ?mcucr ? mcu control regis- ter? on page 44 . note: 1. bod disable only available in picopower devices atmega48pa/88pa/168pa/328p 10.3 idle mode when the sm2...0 bits are written to 000, the sleep instruction makes th e mcu enter idle mode, stopping the cpu but allowing the spi, usart, analog comparator, adc, 2-wire serial interface, timer/counters, watchdog, and the interrupt system to continue operating. this sleep mode basically halts clk cpu and clk flash , while allowing the other clocks to run. idle mode enables the mcu to wake up from external triggered interrup ts as well as internal ones like the timer overflow and usart transmit complete interrupts. if wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by se tting the acd bit in the analog comparator control and status register ? acsr. this will reduce power co nsumption in idle mode. if the adc is enabled, a conver- sion starts automatically when this mode is entered. 10.4 adc noise reduction mode when the sm2...0 bits are written to 001, the sleep instruction makes the mcu enter adc noise reduction mode, stopping the cpu but allowing the adc, the external interrupts, the 2-wire serial interface address watch, timer/counter2 (1) , and the watchdog to continue operating (if enabled). this sleep mode basically halts clk i/o , clk- cpu , and clk flash , while allowing the ot her clocks to run. this improves the noise environment for the adc, enabling higher resolution measurements. if the adc is enabled, a conversion starts automatically when this mode is entered. apart from the adc conversion complete interrupt, only an external reset, a watchdog system reset, a watchdog interrupt, a brown-out reset, a 2-wire serial interface address match, a timer/counter2 interrupt, an spm/eeprom ready interrupt, an external level interrupt on int0 or int1 or a pin change interrupt can wake up the mcu from adc noise reduction mode. note: 1. timer/counter2 will only keep running in asynchronous mode, see ?8-bit timer/counter2 with pwm and asynchro- nous operation? on page 142 for details. 10.5 power-down mode when the sm2...0 bits are written to 010, the sleep in struction makes the mcu ente r power-down mode. in this mode, the external oscillator is stopped , while the external interrupts, the 2-wire serial interf ace address watch, and the watchdog continue operating (if enabled). only an external reset, a watchdog system reset, a watch- dog interrupt, a brown-out reset, a 2-wire serial interface address match, an external level interrupt on int0 or 40 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 int1, or a pin change interrupt can wake up the mcu. th is sleep mode basically halts all generated clocks, allow- ing operation of asynchronous modules only. note: if a level triggered interrupt is used for wake-up from power-down, the required level must be held long enough for the mcu to complete the wake-up to trigger the level interrupt. if the level disappears before the end of the start-up time, the mcu will still wake up, but no interrupt will be generated. ?external interrupts? on page 71 . the start-up time is defined by the sut and cksel fuses as described in ?system clock and clock options? on page 26 . when waking up from power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. this allows the clock to restart and become stable after having been stopped. the wake-up period is defined by the same cksel fuses that define the reset time-out period, as described in ?clock sources? on page 27 . 10.6 power-save mode when the sm2...0 bits are written to 011, the sleep instruction makes the mcu enter power-save mode. this mode is identical to power-down, with one exception: if timer/counter2 is enabled, it will k eep running during sleep. th e device can wake up from either timer overflow or output compare event from timer/counter2 if the corresponding timer/counter2 interrupt enable bits are set in timsk2, and the global interrupt enable bit in sreg is set. if timer/counter2 is not running, power-down mode is recommended instead of power-save mode. the timer/counter2 can be clocked both synchronously and asynchronously in power-save mode. if timer/counter2 is not using the asynchronous clock, the timer/counter oscillator is stopped during sleep. if timer/counter2 is not using the synchronous clock, the cloc k source is stopped during sleep. note that even if the synchronous clock is running in power-save, this clock is only availa ble for timer/counter2. 10.7 standby mode when the sm2...0 bits are 110 and an external crystal/resonator clock option is selected, the sleep instruction makes the mcu enter standby mo de. this mode is identical to power-down with the exception th at the oscillator is kept running. from standby mode, the device wakes up in six clock cycles. 41 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 10.8 extended standby mode when the sm2...0 bits are 111 and an external crystal/resonator clock option is selected, the sleep instruction makes the mcu enter extended standby mode. this mode is i dentical to power-save with the exception that the oscillator is kept runni ng. from extended standb y mode, the device wakes up in six clock cycles. 10.9 power reduction register the power reduction r egister (prr), see ?prr ? power reduction register? on page 44 , provides a method to stop the clock to individual peripherals to reduce power consumption. the current state of the peripheral is frozen and the i/o registers can not be read or written. resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. waking up a module, which is done by clearing the bit in prr, puts the module in the same state as before shutdown. module shutdown can be used in idle mode and active mode to significantly reduce the overall power consump- tion. in all other sleep modes, the clock is already stopped. 10.10 minimizing po wer consumption there are several possibilities to consider when trying to minimize t he power consumption in an avr controlled system. in general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device?s functions are operat ing. all functions not needed should be disabled. in par- ticular, the following modules may need special consider ation when trying to achieve the lowest possible power consumption. 10.10.1 analog to digital converter if enabled, the adc will be enab led in all sleep modes. to save power, the adc should be di sabled before entering any sleep mode. when the adc is turn ed off and on again, the next conver sion will be an extended conversion. refer to ?analog-to-digital converter? on page 242 for details on adc operation. 10.10.2 analog comparator when entering idle mode, the analog comparator should be disabled if not used. when entering adc noise reduction mode, the analog comparator should be disabled. in other sleep modes, the analog comparator is automatically disabled. however, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be disabled in all sleep mo des. otherwise, the intern al voltage reference will be enabled, independent of sleep mode. refer to ?analog comparator? on page 239 for details on how to configure the analog comparator. 10.10.3 brown-out detector if the brown-out detector is not needed by the applicat ion, this module should be turned off. if the brown-out detector is enabled by the bodlevel fuses, it will be enabled in all sleep modes, and hence, always consume power. in the deeper sleep modes, this will contribute significantly to the total current consumpt ion. refer to ?brown-out detection? on page 48 for details on how to configure the brown-out detector. 42 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 10.10.4 internal voltage reference the internal voltage reference will be enabled when needed by the brown-out detection, the analog comparator or the adc. if these modules are disabled as described in the sections above, the internal vo ltage reference will be disabled and it will not be consuming power. when turned on again , the user must allow t he reference to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. refer to ?internal voltage reference? on page 49 for details on the start-up time. 10.10.5 watchdog timer if the watchdog timer is not needed in the application, the module should be turned off. if the watchdog timer is enabled, it will be enab led in all sleep modes and hence always cons ume power. in the d eeper sleep modes, this will contribute significantly to the total current consumption. refer to ?watchdog timer? on page 50 for details on how to configure the watchdog timer. 10.10.6 port pins when entering a sleep mode, all port pins should be configured to use minimum power. the most important is then to ensure that no pins drive resistive loads. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buffers of the device will be disabled. this ensures that no power is consumed by the input logic when not needed. in some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. refer to the section ?digital input enable and sleep modes? on page 80 for details on which pins are enabled. if the input buffer is enabled and the input signal is left floating or have an analog signal level close to v cc /2, the input buffer will use excessive power. for analog input pins, the digital input buffer should be disabled at all times. an analog signal level close to v cc /2 on an input pin can cause significant current even in active mode. digital input buffers can be disabled by writing to the digital input disable registers (didr1 and didr0). refer to ?didr1 ? digital input disable register 1? on page 241 and ?didr0 ? digital input disable register 0? on page 257 for details. 10.10.7 on-chip debug system if the on-chip debug system is enabled by the dwen fuse and the chip enters sleep mode, the main clock source is enabled and hence always consumes power. in the deeper sl eep modes, this will contri bute significantly to the total current consumption. 43 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 10.11 register description 10.11.1 smcr ? sleep mode control register the sleep mode control register contains control bits for power management. ? bits [7:4]: reserved these bits are unused in the at mega48a/pa/88a/pa/168a/p a/328/p, and will always be read as zero. ? bits 3:1 ? sm[2:0]: sleep mode select bits 2, 1, and 0 these bits select between the five available sleep modes as shown in table 10-2 . note: 1. standby mode is only recommended for us e with external crystals or resonators. ? bit 0 ? se: sleep enable the se bit must be written to logic one to make the mcu ente r the sleep mode when the sleep instruction is exe- cuted. to avoid the mcu entering the sleep mode unless it is the programmer?s purpose, it is recommended to write the sleep enable ( se) bit to one just before the execution of the sleep instructio n and to clear it immediately after waking up. bit 76543210 0x33 (0x53) ????sm2sm1sm0sesmcr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 10-2. sleep mode select sm2 sm1 sm0 sleep mode 000idle 0 0 1 adc noise reduction 0 1 0 power-down 0 1 1 power-save 100reserved 101reserved 1 1 0 standby (1) 1 1 1 external standby (1) 44 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 10.11.2 mcucr ? mcu control register ? bit 6 ? bods: bod sleep (1) the bods bit must be written to logic one in order to turn off bod during sleep, see table 10-1 on page 38 . writ- ing to the bods bit is controlled by a timed sequence and an enable bit, bodse in mcucr. to disable bod in relevant sleep modes, both bods and bodse must first be set to one. then, to set the bods bit, bods must be set to one and bodse must be set to zero within four clock cycles. the bods bit is active three clock cycle s after it is set. a sleep instruction must be executed while bods is active in order to turn off the bod for the actual sleep mode. the bods bit is automatically cleared after three clock cycles. ? bit 5 ? bodse: bod sleep enable (1) bodse enables setting of bods control bit, as explained in bods bit description. bod disable is controlled by a timed sequence. note: 1. bods and bodse only available for picopower devices atmega48pa/88pa/168pa/328p 10.11.3 prr ? power reduction register ? bit 7 ? prtwi: power reduction twi writing a logic one to this bit shuts down the twi by stopping the clock to the module. when waking up the twi again, the twi should be re initialized to ensure proper operation. ? bit 6 ? prtim2: power reduction timer/counter2 writing a logic one to this bit shuts down the timer/c ounter2 module in synchronous mode (as2 is 0). when the timer/counter2 is enabled, operation will continue like be fore the shutdown. ? bit 5 ? prtim0: power reduction timer/counter0 writing a logic one to this bit shuts down the timer/counter0 module. when the timer/counter0 is enabled, opera- tion will continue like before the shutdown. ? bit 4 ? reserved this bit is reserved in atmega48a/pa/88a/pa /168a/pa/328/p and will always read as zero. ? bit 3 ? prtim1: power reduction timer/counter1 writing a logic one to this bit shuts down the timer/counter1 module. when the timer/counter1 is enabled, opera- tion will continue like before the shutdown. ? bit 2 ? prspi: power reduction serial peripheral interface if using debugwire on-chip debug system, this bit should not be written to one. writing a logic one to this bit shuts down the serial peripheral interface by stopping th e clock to the module. when waking up the spi again, the spi should be re initialized to ensure proper operation. bit 7 6 5 4 3 2 1 0 0x35 (0x55) ?bods (1) bodse (1) pud ? ? ivsel ivce mcucr read/write r r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 (0x64) prtwi prtim2 prtim0 ? prtim1 prspi prusart0 pradc prr read/write r/w r/w r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 45 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bit 1 ? prusart0: power reduction usart0 writing a logic one to this bit shuts down the usart by stopping the clock to the module. when waking up the usart again, the usart should be re initialized to ensure proper operation. ? bit 0 ? pradc: power reduction adc writing a logic one to this bit shuts down the adc. the adc must be disabled before shut down. the analog com- parator cannot use the adc input mux when the adc is shut down. 46 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 11. system control and reset 11.1 resetting the avr during reset, all i/o registers are set to their initial values, and the program starts execution from the reset vec- tor. for atmega168a/168pa/328/328p the instruction placed at the reset vector must be a jmp ? absolute jump ? instruction to the reset handling routine. for the atmega 48a/48pa and atmega88a/88pa, the instruction placed at the reset vector must be an rjmp ? relative jump ? instruction to the reset handling routine. if the pro- gram never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the re set vector is in the application section while the interrupt vectors are in the boot section or vice versa (atmega88a/88pa/168a/168pa/328/328p only). the circuit diagram in figure 11-1 on page 47 shows the reset logic. table 29-16 on page 312 defines the electrical parameters of the reset circuitry. the i/o ports of the avr are immediately reset to their init ial state when a reset source goes active. this does not require any clock source to be running. after all reset sources have gone inactive, a delay counter is invoked, stretching the inte rnal reset. this allows the power to reach a stable level before normal operation starts. the time-out period of the delay counter is defined by the user through the sut and cksel fuses. the different selections for the delay period are presented in ?clock sources? on page 27 . 11.2 reset sources the atmega48a/pa/88a/pa/168a/pa/328/p has four sources of reset: ? power-on reset. the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ). ? external reset. the mcu is reset wh en a low level is present on the reset pin for longer than the minimum pulse length. ? watchdog system reset. the mcu is reset when the watchdog timer period expires and the watchdog system reset mode is enabled. ? brown-out reset. the mcu is re set when the supply voltage v cc is below the brown-out reset threshold (v bot ) and the brown-out detector is enabled. 47 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 11-1. reset logic 11.3 power-on reset a power-on reset (por) pulse is generated by an on-chi p detection circuit. the dete ction level is defined in ?sys- tem and reset characteristics? on page 312 . the por is activated whenever v cc is below the dete ction level. the por circuit can be used to trigger the start-up reset, as well as to detect a failure in supply voltage. a power-on reset (por) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold voltage invokes t he delay counter, whic h determines how long the device is kept in reset after v cc rise. the reset signal is activated ag ain, without any delay, when v cc decreases below the detection level. figure 11-2. mcu start-up, reset tied to v cc mcu status register (mcusr) brown-out reset circuit bodlevel [2..0] delay counters cksel[3:0] ck timeout wdrf borf extrf porf data b u s clock generator spike filter pull-up resistor watchdog oscillator sut[1:0] power-on reset circuit rstdisbl v reset time-out internal reset t tout v pot v rst cc 48 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 11-3. mcu start-up, reset extended externally 11.4 external reset an external reset is generated by a lo w level on the reset pin. reset pulses longer than the minimum pulse width (see ?system and reset characteristics? on page 312 ) will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold volt- age ? v rst ? on its positive edge, the delay counter starts the mcu after the time-out period ? t tout ? has expired. the external reset can be disabled by the rstdisbl fuse, see table 28-7 on page 287 . figure 11-4. external reset during operation 11.5 brown-out detection atmega48a/pa/88a/pa/168a/pa/328/p has an on-chip brown-out detection (bod) circuit for monitoring the v cc level during operation by comparing it to a fixed trigger level. the trigger level for the bod can be selected by the bodlevel fuses. the trigger le vel has a hysteresis to ensure spike free brown-out detection. the hysteresis on the detection level should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot - v hyst /2.when the bod is enabled, and v cc decreases to a value below the trigger level (v bot- in figure 11-5 on page 49 ), the brown-out reset is immediately activated. when v cc increases above the trigger level (v bot+ in figure 11-5 on page 49 ), the delay counter starts the mcu after the time-out period t tout has expired. the bod circuit will only detect a drop in v cc if the voltage stays below the trigger level for longer than t bod given in ?system and reset characteristics? on page 312 . reset time-out internal reset t tout v pot v rst v cc cc 49 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 11-5. brown-out reset during operation 11.6 watchdog system reset when the watchdog times out, it will gen erate a short reset pulse of one ck cycle duration. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . refer to page 50 for details on operation of the watchdog timer. figure 11-6. watchdog system reset during operation 11.7 internal voltage reference atmega48a/pa/88a/pa/168a/pa/328/p features an internal bandgap reference. this reference is used for brown-out detection, and it can be used as an input to the analog comparator or the adc. 11.7.1 voltage reference enable signals and start-up time the voltage reference has a start-up time that may influence the way it should be used. the start-up time is given in ?system and reset characteristics? on page 312 . to save power, the reference is not always turned on. the ref- erence is on during the following situations: 1. when the bod is enabled (by prog ramming the bodlevel [2:0] fuses). 2. when the bandgap reference is connected to the analog comparator (by setting the acbg bit in acsr). 3. when the adc is enabled. thus, when the bod is not enabled, after setting the acbg bit or enabling the adc, the user must always allow the reference to start up before the output from the analog comparator or adc is used. to reduce power con- sumption in power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering power-down mode. v cc reset time-out internal reset v bot- v bot+ t tout ck cc 50 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 11.8 watchdog timer 11.8.1 features ? clocked from separate on-chip oscillator ? 3 operating modes ?interrupt ? system reset ? interrupt and system reset ? selectable time-out period from 16ms to 8s ? possible hardware fuse watchdog always on (wdton) for fail-safe mode 11.8.2 overview atmega48a/pa/88a/pa/168a/pa/328/p has an enhanced watchdog timer (wdt). the wdt is a timer counting cycles of a separate on-chip 128khz oscillator. the wd t gives an interrupt or a system reset when the counter reaches a given time-out value. in normal operation mode , it is required that the system uses the wdr - watchdog timer reset - instruction to restart th e counter before the time-out value is reached. if the syst em doesn't restart the counter, an interrupt or system reset will be issued. figure 11-7. watchdog timer in interrupt mode, the wdt gives an interrupt when the ti mer expires. this interrupt can be used to wake the device from sleep-modes, and also as a general system ti mer. one example is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected. in system reset mode, the wdt gives a reset when the timer expires. this is typically used to prevent system hang-up in case of runaway code. the third mode, interrupt and system reset mode, comb ines the other two modes by first giving an interrupt and then switch to system re set mode. this mode will for in stance allow a safe shutdown by saving critical param- eters before a system reset. the watchdog always on (wdton) fuse, if programmed, will force the watchdog timer to system reset mode. with the fuse programmed the system reset mode bit (wde) and interrupt mode bit (wdie) are locked to 1 and 0 respectively. to further ensure program security, altera tions to the watchdog set-up must follow timed sequences. the sequence for clearing wde and changing time-out configuration is as follows: 1. in the same operation, write a logic one to the watchdog change enable bit (wdce) and wde. a logic one must be written to wde regardless of the previous value of the wde bit. 2. within the next four clock cycles, write the wde and watchdog prescaler bits (wdp) as desired, but with the wdce bit cleared. this must be done in one operation. 128khz oscillator osc/2k osc/4k osc/8k osc/16k osc/32k osc/64k osc/128k osc/256k osc/512k osc/1024k wdp0 wdp1 wdp2 wdp3 watchdog reset wde wdif wdie mcu reset interrupt 51 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 the following code example shows one assembly and one c function for turning off the watchdog timer. the example assumes that inte rrupts are controlled (e .g. by disabling interrupts globa lly) so that no interrupts will occur during the execution of these functions. 52 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. see ?about code examples? on page 7. note: if the watchdog is accidentally enabled, for exampl e by a runaway pointer or brown-out condition, the device will be reset and the watchdog timer will stay enabled. if the co de is not set up to handle the watchdog, this might lead to an eternal loop of time-out resets. to avoid this situation, the application software should always clear the watchdog system reset flag (wdrf) and the wde control bit in the initialization routine, even if the watchdog is not in use. assembly code example (1) wdt_off: ; turn off global interrupt cli ; reset watchdog timer wdr ; clear wdrf in mcusr in r16, mcusr andi r16, (0xff & (0< 55 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 itself, as this might compromise the safety-function of the watchdog system reset mode. if the interrupt is not exe- cuted before the next time-ou t, a system reset will be applied. note: 1. wdton fuse set to ?0? means programmed and ?1? means unprogrammed. ? bit 4 ? wdce: watchdog change enable this bit is used in timed sequences fo r changing wde and prescaler bits. to clear the wde bit, and/or change the prescaler bits, wdce must be set. once written to one, ha rdware will clear wdce af ter four clock cycles. ? bit 3 ? wde: watchdog system reset enable wde is overridden by wdrf in mcusr. this means that wde is always set when wdrf is set. to clear wde, wdrf must be cleared first. this feature ensures mult iple resets during conditions causing failure, and a safe start-up after the failure. ? bit 5, 2:0 - wdp[3:0]: watchdog timer prescaler 3, 2, 1 and 0 the wdp[3:0] bits determine the watchdog timer presca ling when the watchdog timer is running. the different prescaling values and their corresponding time-out periods are shown in table 11-2 on page 55 . table 11-1. watchdog timer configuration wdton (1) wde wdie mode action on time-out 1 0 0 stopped none 1 0 1 interrupt mode interrupt 1 1 0 system reset mode reset 111 interrupt and system reset mode interrupt, then go to system reset mode 0 x x system reset mode reset table 11-2. watchdog timer prescale select wdp3 wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 5.0v 0 0 0 0 2k (2048) cycles 16ms 0 0 0 1 4k (4096) cycles 32ms 0 0 1 0 8k (8192) cycles 64ms 0 0 1 1 16k (16384) cycles 0.125 s 0 1 0 0 32k (32768) cycles 0.25 s 0 1 0 1 64k (65536) cycles 0.5 s 0 1 1 0 128k (131072) cycles 1.0 s 0 1 1 1 256k (262144) cycles 2.0 s 1 0 0 0 512k (524288) cycles 4.0 s 1 0 0 1 1024k (1048576) cycles 8.0 s 56 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 1010 reserved 1011 1100 1101 1110 1111 table 11-2. watchdog timer prescale select (continued) wdp3 wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 5.0v 57 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 12. interrupts this section describes the specifics of the interrupt handling as performed in atmega48a/pa/88a/pa/168a/pa/328/p. for a general expl anation of the avr interrupt handling, refer to ?reset and interrupt handling? on page 13 . the interrupt vectors in atmega 48a/48pa, atmega88a/88pa, atmega168a/168pa and atmega328/328p are generally the same, with the following differences: ? each interrupt vector occupies two instruction words in atmega168a/168pa and atmega328/328p, and one instruction word in atmega 48a/48pa and atmega88a/88pa. ? atmega 48a/48pa does not have a separate boot loader section. in atmega88a/88pa, atmega168a/168pa and atmega328/328p, the reset vector is affected by the bootrst fuse, and the interrupt vector start address is affected by the ivsel bit in mcucr. 12.1 interrupt vectors in atmega48a and atmega48pa table 12-1. reset and interrupt vectors in atmega48a and atmega48pa vector no. program address source interrupt definition 1 0x000 reset external pin, power-on reset, brown-out reset and watchdog system reset 2 0x001 int0 external interrupt request 0 3 0x002 int1 external interrupt request 1 4 0x003 pcint0 pin change interrupt request 0 5 0x004 pcint1 pin change interrupt request 1 6 0x005 pcint2 pin change interrupt request 2 7 0x006 wdt watchdog time-out interrupt 8 0x007 timer2 compa timer/c ounter2 compare match a 9 0x008 timer2 compb timer/c ounter2 compare match b 10 0x009 timer2 ovf timer/counter2 overflow 11 0x00a timer1 capt timer/counter1 capture event 12 0x00b timer1 compa timer/counter1 compare match a 13 0x00c timer1 compb timer/c outner1 compare match b 14 0x00d timer1 ovf timer/counter1 overflow 15 0x00e timer0 compa timer/counter0 compare match a 16 0x00f timer0 compb timer/c ounter0 compare match b 17 0x010 timer0 ovf timer/counter0 overflow 18 0x011 spi, stc spi serial transfer complete 19 0x012 usart, rx usart rx complete 20 0x013 usart, udre usart, data register empty 21 0x014 usart, tx usart, tx complete 22 0x015 adc adc conversion complete 23 0x016 ee ready eeprom ready 58 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 the most typical and general program setup for the reset and interrupt vector addresses in atmega 48a/48pa is: address labels code comments 0x000 rjmp reset ; reset handler 0x001 rjmp ext_int0 ; irq0 handler 0x002 rjmp ext_int1 ; irq1 handler 0x003 rjmp pcint0 ; pcint0 handler 0x004 rjmp pcint1 ; pcint1 handler 0x005 rjmp pcint2 ; pcint2 handler 0x006 rjmp wdt ; watchdog timer handler 0x007 rjmp tim2_compa ; timer2 compare a handler 0x008 rjmp tim2_compb ; timer2 compare b handler 0x009 rjmp tim2_ovf ; timer2 overflow handler 0x00a rjmp tim1_capt ; timer1 capture handler 0x00b rjmp tim1_compa ; timer1 compare a handler 0x00c rjmp tim1_compb ; timer1 compare b handler 0x00d rjmp tim1_ovf ; timer1 overflow handler 0x00e rjmp tim0_compa ; timer0 compare a handler 0x00f rjmp tim0_compb ; timer0 compare b handler 0x010 rjmp tim0_ovf ; timer0 overflow handler 0x011 rjmp spi_stc ; spi transfer complete handler 0x012 rjmp usart_rxc ; usart, rx complete handler 0x013 rjmp usart_udre ; usart, udr empty handler 0x014 rjmp usart_txc ; usart, tx complete handler 0x015 rjmp adc ; adc conversion complete handler 0x016 rjmp ee_rdy ; eeprom ready handler 0x017 rjmp ana_comp ; analog comparator handler 0x018 rjmp twi ; 2-wire serial interface handler 0x019 rjmp spm_rdy ; store program memory ready handler ; 0x01areset: ldi r16, high(ramend); main program start 0x01b out sph,r16 ; set stack pointer to top of ram 0x01c ldi r16, low(ramend) 0x01d out spl,r16 0x01e sei ; enable interrupts 0x01f 59 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 12.2 interrupt vectors in atmega88a and atmega88pa notes: 1. when the bootrst fuse is pr ogrammed, the device will jump to t he boot loader address at reset, see ?boot loader sup- port ? read-while-write self-programming? on page 269 . 2. when the ivsel bit in mcucr is set, interrupt vectors will be moved to the start of the boot flash section. the address of each interrupt vector will then be the address in this table added to the start address of the boot flash section. table 12-3 on page 60 shows reset and interrupt vectors placement for the various combinations of bootrst and ivsel settings. if the program neve r enables an interrupt so urce, the interrupt vector s are not used, and reg- ular program code can be placed at these lo cations. this is also the case if th e reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. table 12-2. reset and interrupt vectors in atmega88a and atmega88pa vector no. program address (2) source interrup t definition 1 0x000 (1) reset external pin, power-on reset, brown-out reset and watchdog system reset 2 0x001 int0 external interrupt request 0 3 0x002 int1 external interrupt request 1 4 0x003 pcint0 pin change interrupt request 0 5 0x004 pcint1 pin change interrupt request 1 6 0x005 pcint2 pin change interrupt request 2 7 0x006 wdt watchdog time-out interrupt 8 0x007 timer2 compa timer /counter2 compare match a 9 0x008 timer2 compb timer /counter2 compare match b 10 0x009 timer2 ovf timer/counter2 overflow 11 0x00a timer1 capt timer/counter1 capture event 12 0x00b timer1 compa timer/counter1 compare match a 13 0x00c timer1 compb timer/coutner1 compare match b 14 0x00d timer1 ovf timer/counter1 overflow 15 0x00e timer0 compa timer/counter0 compare match a 16 0x00f timer0 compb timer /counter0 compare match b 17 0x010 timer0 ovf timer/counter0 overflow 18 0x011 spi, stc spi serial transfer complete 19 0x012 usart, rx usart rx complete 20 0x013 usart, udre usart, data register empty 21 0x014 usart, tx usart, tx complete 22 0x015 adc adc conversion complete 23 0x016 ee ready eeprom ready 24 0x017 analog comp analog comparator 25 0x018 twi 2-wire serial interface 26 0x019 spm ready store program memory ready 60 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. the boot reset address is shown in table 27-7 on page 280 . for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. the most typical and general program setup for the reset and interrupt vector addresses in atmega88a/88pa is: address labels code comments 0x000 rjmp reset ; reset handler 0x001 rjmp ext_int0 ; irq0 handler 0x002 rjmp ext_int1 ; irq1 handler 0x003 rjmp pcint0 ; pcint0 handler 0x004 rjmp pcint1 ; pcint1 handler 0x005 rjmp pcint2 ; pcint2 handler 0x006 rjmp wdt ; watchdog timer handler 0x007 rjmp tim2_compa ; timer2 compare a handler 0x008 rjmp tim2_compb ; timer2 compare b handler 0x009 rjmp tim2_ovf ; timer2 overflow handler 0x00a rjmp tim1_capt ; timer1 capture handler 0x00b rjmp tim1_compa ; timer1 compare a handler 0x00c rjmp tim1_compb ; timer1 compare b handler 0x00d rjmp tim1_ovf ; timer1 overflow handler 0x00e rjmp tim0_compa ; timer0 compare a handler 0x00f rjmp tim0_compb ; timer0 compare b handler 0x010 rjmp tim0_ovf ; timer0 overflow handler 0x011 rjmp spi_stc ; spi transfer complete handler 0x012 rjmp usart_rxc ; usart, rx complete handler 0x013 rjmp usart_udre ; usart, udr empty handler 0x014 rjmp usart_txc ; usart, tx complete handler 0x015 rjmp adc ; adc conversion complete handler 0x016 rjmp ee_rdy ; eeprom ready handler 0x017 rjmp ana_comp ; analog comparator handler 0x018 rjmp twi ; 2-wire serial interface handler 0x019 rjmp spm_rdy ; store program memory ready handler ; 0x01areset: ldi r16, high(ramend); main program start 0x01b out sph,r16 ; set stack pointer to top of ram 0x01c ldi r16, low(ramend) 0x01d out spl,r16 0x01e sei ; enable interrupts 0x01f 61 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 when the bootrst fuse is unprogrammed, the boot section size set to 2kbytes and the ivsel bit in the mcucr register is set before any interrupts are enabled , the most typical and gener al program setup for the reset and interrupt vector addresses in atmega88a/88pa is: address labels code comments 0x000 reset: ldi r16,high(ramend); main program start 0x001 out sph,r16 ; set stack pointer to top of ram 0x002 ldi r16,low(ramend) 0x003 out spl,r16 0x004 sei ; enable interrupts 0x005 62 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 0xc1d out spl,r16 0xc1e sei ; enable interrupts 0xc1f 63 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ular program code can be placed at these lo cations. this is also the case if th e reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. note: 1. the boot reset address is shown in table 27-7 on page 280 . for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. the most typical and general program setup for the reset and interrupt vector addresses in atmega168a/168pa is: address labels code comments 0x0000 jmp reset ; reset handler 0x0002 jmp ext_int0 ; irq0 handler 0x0004 jmp ext_int1 ; irq1 handler 0x0006 jmp pcint0 ; pcint0 handler 0x0008 jmp pcint1 ; pcint1 handler 0x000a jmp pcint2 ; pcint2 handler 0x000c jmp wdt ; watchdog timer handler 0x000e jmp tim2_compa ; timer2 compare a handler 0x0010 jmp tim2_compb ; timer2 compare b handler 0x0012 jmp tim2_ovf ; timer2 overflow handler 0x0014 jmp tim1_capt ; timer1 capture handler 0x0016 jmp tim1_compa ; timer1 compare a handler 0x0018 jmp tim1_compb ; timer1 compare b handler 0x001a jmp tim1_ovf ; timer1 overflow handler 0x001c jmp tim0_compa ; timer0 compare a handler 0x001e jmp tim0_compb ; timer0 compare b handler 0x0020 jmp tim0_ovf ; timer0 overflow handler 0x0022 jmp spi_stc ; spi transfer complete handler 0x0024 jmp usart_rxc ; usart, rx complete handler 0x0026 jmp usart_udre ; usart, udr empty handler 0x0028 jmp usart_txc ; usart, tx complete handler 0x002a jmp adc ; adc conversion complete handler 0x002c jmp ee_rdy ; eeprom ready handler 0x002e jmp ana_comp ; analog comparator handler 0x0030 jmp twi ; 2-wire serial interface handler 0x0032 jmp spm_rdy ; store program memory ready handler ; 0x0033reset: ldi r16, high(ramend); main program start 0x0034 out sph,r16 ; set stack pointer to top of ram 0x0035 ldi r16, low(ramend) 0x0036 out spl,r16 0x0037 sei ; enable interrupts table 12-5. reset and interrupt vectors placement in atmega168a and atmega168pa (1) bootrst ivsel reset address inter rupt vectors start address 1 0 0x000 0x002 1 1 0x000 boot reset address + 0x0002 0 0 boot reset address 0x002 0 1 boot reset address boot reset address + 0x0002 64 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 0x0038 65 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 0x1c33 reset: ldi r16,high(ramend); main program start 0x1c34 out sph,r16 ; set stack pointer to top of ram 0x1c35 ldi r16,low(ramend) 0x1c36 out spl,r16 0x1c37 sei ; enable interrupts 0x1c38 66 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 2. when the ivsel bit in mcucr is set, interrupt vectors will be moved to the start of the boot flash section. the address of each interrupt vector will then be the address in this table added to the start address of the boot flash section. table 12-7 on page 66 shows reset and interrupt vectors placement for the various combinations of bootrst and ivsel settings. if the program neve r enables an interrupt so urce, the interrupt vector s are not used, and reg- ular program code can be placed at these lo cations. this is also the case if th e reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. note: 1. the boot reset address is shown in table 27-7 on page 280 . for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. the most typical and general program setup for the reset and interrupt vector addresses in atmega328/328p is: address labels code comments 0x0000 jmp reset ; reset handler 0x0002 jmp ext_int0 ; irq0 handler 0x0004 jmp ext_int1 ; irq1 handler 0x0006 jmp pcint0 ; pcint0 handler 0x0008 jmp pcint1 ; pcint1 handler 0x000a jmp pcint2 ; pcint2 handler 0x000c jmp wdt ; watchdog timer handler 0x000e jmp tim2_compa ; timer2 compare a handler 0x0010 jmp tim2_compb ; timer2 compare b handler 0x0012 jmp tim2_ovf ; timer2 overflow handler 0x0014 jmp tim1_capt ; timer1 capture handler 0x0016 jmp tim1_compa ; timer1 compare a handler 0x0018 jmp tim1_compb ; timer1 compare b handler 0x001a jmp tim1_ovf ; timer1 overflow handler 0x001c jmp tim0_compa ; timer0 compare a handler 0x001e jmp tim0_compb ; timer0 compare b handler 0x0020 jmp tim0_ovf ; timer0 overflow handler 0x0022 jmp spi_stc ; spi transfer complete handler 0x0024 jmp usart_rxc ; usart, rx complete handler 0x0026 jmp usart_udre ; usart, udr empty handler 0x0028 jmp usart_txc ; usart, tx complete handler 0x002a jmp adc ; adc conversion complete handler 0x002c jmp ee_rdy ; eeprom ready handler 0x002e jmp ana_comp ; analog comparator handler 0x0030 jmp twi ; 2-wire serial interface handler 0x0032 jmp spm_rdy ; store program memory ready handler ; 0x0033reset: ldi r16, high(ramend); main program start 0x0034 out sph,r16 ; set stack pointer to top of ram table 12-7. reset and interrupt vectors placement in atmega328 and atmega328p (1) bootrst ivsel reset address inter rupt vectors start address 1 0 0x000 0x002 1 1 0x000 boot reset address + 0x0002 0 0 boot reset address 0x002 0 1 boot reset address boot reset address + 0x0002 67 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 0x0035 ldi r16, low(ramend) 0x0036 out spl,r16 0x0037 sei ; enable interrupts 0x0038 68 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 0x3c32 jmp spm_rdy ; store program memory ready handler ; 0x3c33 reset: ldi r16,high(ramend); main program start 0x3c34 out sph,r16 ; set stack pointer to top of ram 0x3c35 ldi r16,low(ramend) 0x3c36 out spl,r16 0x3c37 sei ; enable interrupts 0x3c38 69 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 12.5 register description 12.5.1 moving interrupts between application and b oot space, atmega88a/88pa, atmega168a/168pa and atmega328/328p the mcu control register controls the placement of the interrupt vector table. mcucr ? mcu control register note: 1. bods and bodse only available for picopower devices atmega48pa/88pa/168pa/328p ? bit 1 ? ivsel: interrupt vector select when the ivsel bit is cleared (zero), the interrupt vectors are placed at the start of the flash memory. when this bit is set (one), the interrupt vectors are moved to the beginning of the boot loader section of the flash. the actual address of the start of the boot flash section is determined by the bootsz fuses. refer to the section ?boot loader support ? read-while-write self-programming? on page 269 for details. to avoid unintentional changes of interrupt vector tables, a spec ial write procedure must be fo llowed to change the ivsel bit: a. write the interrupt vector change enable (ivce) bit to one. b. within four cycles, write the desired value to ivsel while writing a zero to ivce. interrupts will auto matically be disabled while this sequence is ex ecuted. interrupts are di sabled in the cycle ivce is set, and they remain disa bled until after the instruction following the wr ite to ivsel. if ivsel is not written, inter- rupts remain disabled for four cycles. the i-bit in the status register is unaffected by the automatic disabling. note: if interrupt vectors are placed in the boot loader section and boot lock bit blb02 is programmed, interrupts are dis- abled while executing from the applicati on section. if interrupt vectors are pl aced in the application section and boot lock bit blb12 is programed, interrupts are disabled while executing from the boot loader section. refer to the sec- tion ?boot loader support ? read-while-write self-programming? on page 269 for details on boot lock bits. ? bit 0 ? ivce: interrupt vector change enable the ivce bit must be written to logi c one to enable change of the ivsel bi t. ivce is cleared by hardware four cycles after it is written or when ivsel is written. settin g the ivce bit will disable in terrupts, as explained in the ivsel description above. see code example below. bit 76 5 43210 0x35 (0x55) ? bods (1) bodse (1) pud ? ? ivsel ivce mcucr read/write r r/w r/w r/w r r r/w r/w initial value00 0 00000 70 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 assembly code example move_interrupts: ; enable change of interrupt vectors ldi r16, (1< 72 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 13.2 register description 13.2.1 eicra ? external interrupt control register a the external interrupt control register a contains control bits for interrupt sense control. ? bit 7:4 ? reserved these bits are unused bits in the atmega48a/pa/ 88a/pa/168a/pa/328/p, and w ill always read as zero. ? bit 3, 2 ? isc11, isc10: interrupt sense control 1 bit 1 and bit 0 the external interrupt 1 is activated by the external pi n int1 if the sreg i-flag and the corresponding interrupt mask are set. the level and edges on the external int1 pin that activate the interrupt are defined in table 13-1 . the value on the int1 pin is sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longer than one clock period will genera te an interrupt. shorter pulses are not guaranteed to generate an interrupt. if low level interrupt is sele cted, the low level must be held until the completion of the currently executing instruction to generate an interrupt. ? bit 1, 0 ? isc01, isc00: interrupt sense control 0 bit 1 and bit 0 the external interrupt 0 is activated by the external pi n int0 if the sreg i-flag and the corresponding interrupt mask are set. the level and edges on the external int0 pin that activate the interrupt are defined in table 13-2 . the value on the int0 pin is sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longer than one clock period will genera te an interrupt. shorter pulses are not guaranteed to generate an interrupt. if low level interrupt is sele cted, the low level must be held until the completion of the currently executing instruction to generate an interrupt. bit 76543210 (0x69) ? ? ? ? isc11 isc10 isc01 isc00 eicra read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 13-1. interrupt 1 sense control isc11 isc10 description 0 0 the low level of int1 generates an interrupt request. 0 1 any logical change on int1 generates an interrupt request. 1 0 the falling edge of int1 generates an interrupt request. 1 1 the rising edge of int1 generates an interrupt request. table 13-2. interrupt 0 sense control isc01 isc00 description 0 0 the low level of int0 generates an interrupt request. 0 1 any logical change on int0 generates an interrupt request. 1 0 the falling edge of int0 generates an interrupt request. 1 1 the rising edge of int0 generates an interrupt request. 73 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 13.2.2 eimsk ? external interrupt mask register ? bit 7:2 ? reserved these bits are unused bits in the atmega48a/pa/ 88a/pa/168a/pa/328/p, and w ill always read as zero. ? bit 1 ? int1: external interrupt request 1 enable when the int1 bit is set (one) and the i-bit in the status register (sreg) is set (one), the external pin interrupt is enabled. the interrupt sense control1 bits 1/0 (isc11 and isc10) in the external interrupt control register a (eicra) define whether the external interrupt is activated on rising and/or falling edge of the int1 pin or level sensed. activity on the pin will cause an interrupt request even if int1 is co nfigured as an ou tput. the correspond- ing interrupt of external interrupt request 1 is executed from the int1 interrupt vector. ? bit 0 ? int0: external interrupt request 0 enable when the int0 bit is set (one) and the i-bit in the status register (sreg) is set (one), the external pin interrupt is enabled. the interrupt sense control0 bits 1/0 (isc01 and isc00) in the external interrupt control register a (eicra) define whether the external interrupt is activated on rising and/or falling edge of the int0 pin or level sensed. activity on the pin will cause an interrupt request even if int0 is co nfigured as an ou tput. the correspond- ing interrupt of external interrupt request 0 is executed from the int0 interrupt vector. 13.2.3 eifr ? external interrupt flag register ? bit 7:2 ? reserved these bits are unused bits in the atmega48a/pa/ 88a/pa/168a/pa/328/p, and w ill always read as zero. ? bit 1 ? intf1: external interrupt flag 1 when an edge or logic change on the int1 pin triggers an interrupt request, intf1 becomes set (one). if the i-bit in sreg and the int1 bit in eimsk are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is ex ecuted. alternatively, the flag can be cleared by writing a logical one to it. this flag is always cleared when int1 is configured as a level interrupt. ? bit 0 ? intf0: external interrupt flag 0 when an edge or logic change on the int0 pin triggers an interrupt request, intf0 becomes set (one). if the i-bit in sreg and the int0 bit in eimsk are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is ex ecuted. alternatively, the flag can be cleared by writing a logical one to it. this flag is always cleared when int0 is configured as a level interrupt. 13.2.4 pcicr ? pin change interrupt control register bit 76543210 0x1d (0x3d) ??????int1int0eimsk read/write rrrrrrr/wr/w initial value00000000 bit 76543210 0x1c (0x3c) ??????intf1intf0eifr read/write rrrrrrr/wr/w initial value00000000 bit 76543210 (0x68) ?????pcie2pcie1pcie0pcicr read/write rrrrrr/wr/wr/w initial value00000000 74 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bit 7:3 ? reserved these bits are unused bits in the atmega48a/pa/ 88a/pa/168a/pa/328/p, and w ill always read as zero. ? bit 2 ? pcie2: pin change interrupt enable 2 when the pcie2 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 2 is enabled. any change on any enabled pcint[23:16] pin will cause an interrupt. the co rresponding inte rrupt of pin change interrupt request is executed from the pci2 in terrupt vector. pcint[23:16] pins are enabled individually by the pcmsk2 register. ? bit 1 ? pcie1: pin change interrupt enable 1 when the pcie1 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 1 is enabled. any change on any enabled pcint[14:8] pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci1 inte rrupt vector. pcint[14:8] pins are enabled individually by the pcmsk1 register. ? bit 0 ? pcie0: pin change interrupt enable 0 when the pcie0 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 0 is enabled. any change on any enabled pcint[7:0] pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci0 interr upt vector. pcint[7:0] pins are enabled individually by the pcmsk0 register. 13.2.5 pcifr ? pin change interrupt flag register ? bit 7:3 ? reserved these bits are unused bits in the atmega48a/pa/ 88a/pa/168a/pa/328/p, and w ill always read as zero. ? bit 2 ? pcif2: pin change interrupt flag 2 when a logic change on any pcint[23:16] pin triggers an interrupt request, pcif2 becomes set (one). if the i-bit in sreg and the pcie2 bit in pcicr are se t (one), the mcu will jump to the co rresponding interrup t vector. the flag is cleared when the interrupt routine is ex ecuted. alternatively, the flag can be cleared by writing a logical one to it. ? bit 1 ? pcif1: pin change interrupt flag 1 when a logic change on any pcint[14:8] pin triggers an interrupt request, pcif1 becomes set (one). if the i-bit in sreg and the pcie1 bit in pcicr are se t (one), the mcu will jump to the co rresponding interrup t vector. the flag is cleared when the interrupt routine is ex ecuted. alternatively, the flag can be cleared by writing a logical one to it. bit 76543210 0x1b (0x3b) ?????pcif2pcif1pcif0pcifr read/write rrrrrr/wr/wr/w initial value00000000 75 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bit 0 ? pcif0: pin change interrupt flag 0 when a logic change on any pcint[7:0] pin triggers an interrupt request, pcif0 becomes set (one). if the i-bit in sreg and the pcie0 bit in pcicr are se t (one), the mcu will jump to the co rresponding interrup t vector. the flag is cleared when the interrupt routine is ex ecuted. alternatively, the flag can be cleared by writing a logical one to it. 13.2.6 pcmsk2 ? pin change mask register 2 ? bit 7:0 ? pcint[23:16]: pin change enable mask 23...16 each pcint[23:16]-bit selects whether pin change interrupt is enabled on the corresponding i/o pin. if pcint[23:16] is set and the pcie2 bit in pcicr is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint[23:16] is cleared, pin change inte rrupt on the corresponding i/o pin is disabled. 13.2.7 pcmsk1 ? pin change mask register 1 ? bit 7 ? reserved this bit is an unused bit in t he atmega48a/pa/88a/pa/1 68a/pa/328/p, and will always read as zero. ? bit 6:0 ? pcint[14:8]: pin change enable mask 14...8 each pcint[14:8]-bit selects whether pin change interrupt is enabled on the corresponding i/o pin. if pcint[14:8] is set and the pcie1 bit in pcicr is set, pin ch ange interrupt is enabled on the corresponding i/o pin. if pcint[14:8] is cleared, pin change interrup t on the corresponding i/o pin is disabled. 13.2.8 pcmsk0 ? pin change mask register 0 ? bit 7:0 ? pcint[7:0]: pin change enable mask 7...0 each pcint[7:0] bit selects whether pin change interrupt is enabled on the corresponding i/o pin. if pcint[7:0] is set and the pcie0 bit in pcicr is set, pin change interr upt is enabled on the corresponding i/o pin. if pcint[7:0] is cleared, pin change interrupt on the corresponding i/o pin is disabled. bit 76543210 (0x6d) pcint23 pcint22 pcint21 pcint20 pcint19 pcint18 pcint17 pcint16 pcmsk2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x6c) ? pcint14 pcint13 pcint12 pcint11 pcint10 pcint9 pcint8 pcmsk1 read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x6b) pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 pcmsk0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 76 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 14. i/o-ports 14.1 overview all avr ports have true read-modify-write functionality when used as general digital i/o ports. this means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the sbi and cbi instructions. the same applies when changing drive value (if configured as output) or enabling/dis- abling of pull-up resistors (if configured as input). each output buffer has symmetrical drive characteristics with both high sink and source capability. the pin driver is strong enough to dr ive led displa ys directly. all port pins have individually selectable pull-up resi stors with a supply-voltage invariant re sistance. all i/o pins have protection diodes to both v cc and ground as indicated in figure 14-1 . refer to ?electrical characteristics ? (ta = -40c to 85c)? on page 303 for a complete list of parameters. figure 14-1. i/o pin equivalent schematic all registers and bit references in this section are written in general form. a lower case ?x? represents the number- ing letter for the port, and a lower case ?n? represents the bit number. however, when using the register or bit defines in a program, the precise form must be used. for example, portb3 for bit no. 3 in port b, here docu- mented generally as portxn. the physical i/o registers and bit locations are listed in ?register description? on page 92 . three i/o memory address locations are allocated for each port, one each for the data register ? portx, data direction register ? ddrx, and the port input pins ? pinx. the port input pins i/o location is read only, while the data register and the data direction register are read/wri te. however, writing a logic one to a bit in the pinx reg- ister, will result in a toggle in the corresponding bit in the data register. in addition , the pull-up disable ? pud bit in mcucr disables the pull-up function for all pins in all ports when set. using the i/o port as general digital i/o is described in ?ports as general digital i/o? on page 77 . most port pins are multiplexed with alternate functions for the peripheral features on the device. how each alternate function inter- feres with the port pin is described in ?alternate port functions? on page 81 . refer to the individual module sections for a full description of the alternate functions. note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital i/o. c pin logic r pu see figure "general digital i/o" for details pxn 77 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 14.2 ports as gener al digital i/o the ports are bi-directional i/o ports with optional internal pull-ups. figure 14-2 shows a functional description of one i/o-port pin, here generically called pxn. figure 14-2. general digital i/o (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. 14.2.1 configuring the pin each port pin consists of three register bits: ddxn, portxn, and pinxn. as shown in ?register description? on page 92 , the ddxn bits are accessed at the ddrx i/o address, the portxn bits at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects the direction of this pin. if ddxn is written logic one, pxn is configured as an output pin. if ddxn is written logic zero, pxn is configured as an input pin. if portxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. to switch the pull-up resistor off, portxn has to be written logic ze ro or the pin has to be configured as an output pin. the port pins are tri-stated when reset condition becomes active, even if no clocks are running. if portxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). if portxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 14.2.2 toggling the pin writing a logic one to pinxn toggles the value of portxn, independent on the value of ddrxn. note that the sbi instruction can be used to toggle one single bit in a port. clk rpx rrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data b u s sleep sleep: sleep control pxn i/o wpx 0 1 wrx wpx: write pinx register 78 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 14.2.3 switching between input and output when switching between tri-state ({ddxn, portxn} = 0b00) and output high ({ddxn, portxn} = 0b11), an inter- mediate state with either pull-up enabled {ddxn, port xn} = 0b01) or output low ({ddxn, portxn} = 0b10) must occur. normally, the pull-up enabled state is fully acceptable, as a high-impeda nce environment will not notice the difference between a strong high driver and a pull-up. if this is not the case, the pud bit in the mcucr register can be set to disable a ll pull-ups in all ports. switching between input with pull-up and output low generates the same problem. the user must use either the tri- state ({ddxn, portxn} = 0b00) or the output high state ({ddxn, portxn} = 0b11) as an intermediate step. table 14-1 summarizes the control signals for the pin value. 14.2.4 reading the pin value independent of the setting of data direction bit ddxn, the port pin can be read through the pinxn register bit. as shown in figure 14-2 , the pinxn register bit and the preceding latc h constitute a synchronizer. this is needed to avoid metastability if the physical pin changes value near t he edge of the internal clock, but it also introduces a delay. figure 14-3 shows a timing diagram of the synchronization when reading an externally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. figure 14-3. synchronization when reading an externally applied pin value consider the clock period starting shortly after the first falling edge of the system clock. the latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ?sync latch? signal. the signal value is latche d when the system clock goes low. it is clocked into the pinxn register at the succeeding positive clock edge. as indicated by the tw o arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ? and 1? system cl ock period depend ing upon the time of assertion. table 14-1. port pin configurations ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input no tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pulled low. 0 1 1 input no tri-state (hi-z) 1 0 x output no output low (sink) 1 1 x output no output high (source) xxx in r17, pinx 0x00 0xff instructions sync latch pinxn r17 xxx system clk t pd, max t pd, min 79 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 when reading back a software assigned pin value, a nop instruction must be inserted as indicated in figure 14-4 . the out instruction sets the ?sync latch? signal at the positive edge of the clock. in this case, the delay tpd through the synchronizer is 1 system clock period. figure 14-4. synchronization when reading a software assigned pin value the following code example shows how to set port b pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. the resulting pin values are read back again, but as pre- viously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. out portx, r16 nop in r17, pinx 0xff 0x00 0xff system clk r16 instructions sync latch pinxn r17 t pd 80 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. for the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits ar e correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. 14.2.5 digital input enable and sleep modes as shown in figure 14-2 , the digital input signal can be clamped to ground at the input of the schmitt trigger. the signal denoted sleep in the figure, is set by the mcu sleep controller in power-down mode, power-save mode, and standby mode to avoid high power consumption if some i nput signals are left floating, or have an analog signal level close to v cc /2. sleep is overridden for port pins enabled as external inte rrupt pins. if the external in terrupt request is not enabled, sleep is active also for these pins. sl eep is also overridden by various other alternate function s as described in ?alternate port functions? on page 81 . if a logic high level (?one?) is present on an asynchronous external interrupt pin configured as ?interrupt on rising edge, falling edge, or any logic change on pin? while the external interrupt is not enabled, the corresponding external interrupt flag will be set when resuming from the above mentioned sl eep mode, as the cl amping in these sleep mode produces the requested logic change. 14.2.6 unconnected pins if some pins are unused, it is recommended to ensure that these pins have a defined level. even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where t he digital inputs are enabled (reset, active mode and idle mode). assembly code example (1) ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16,(1< 82 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 table 14-2 summarizes the function of the overriding signals. the pin and port indexes from figure 14-5 on page 81 are not shown in the succeeding tables. the overriding signals are generated internally in the modules having the alternate function. the following subsections shortly describe the alternate functi ons for each port, and relate the overriding signals to the alternate function. refer to the alternat e function description for further details. table 14-2. generic description of overriding signals for alternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when {ddxn, portxn, pud} = 0b010. puov pull-up override value if puoe is set, the pull-up is enabled/disabled when puov is set/cleared, regardless of the setting of the ddxn, portxn, and pud register bits. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cleared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output driver is enabled/disabled when ddov is set/cleared, regardless of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital input enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital input is enabled/disabled when dieov is set/cleared, regardless of the mcu state (normal mode, sleep mode). di digital input this is the digital input to alternate functions. in the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. unless the digital input is used as a clock source, the module with th e alternate function will use its own synchronizer. aio analog input/output this is the analog input/output to/from alternate functions. the signal is connected directly to the pad, and can be used bi- directionally. 83 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 14.3.1 alternate functions of port b the port b pins with alternate functions are shown in table 14-3 . the alternate pin configuration is as follows: ? xtal2/tosc2/pcint7 ? port b, bit 7 xtal2: chip clock oscillator pin 2. used as clock pin for crystal oscillat or or low-frequency crystal oscillator. when used as a clock pin, the pin can not be used as an i/o pin. tosc2: timer oscillator pin 2. used only if internal calib rated rc oscillator is selected as chip clock source, and the asynchronous timer is enabled by the correct setting in assr. when the as2 bit in assr is set (one) and the exclk bit is cleared (zero) to enable asynchronous cloc king of timer/counter2 using the crystal oscillator, pin pb7 is disconnected from the port, and becomes the inverting output of the oscillator amplifier. in this mode, a crystal oscillator is connected to this pin, and the pin ca nnot be used as an i/o pin. pcint7: pin change interrupt source 7. the pb7 pin can serve as an external interrupt source. if pb7 is used as a clock pin, ddb7, portb7 and pinb7 will all read 0. ? xtal1/tosc1/pcint6 ? port b, bit 6 xtal1: chip clock oscillator pin 1. used for all chip cl ock sources except internal calibrated rc oscillator. when used as a clock pin, the pin can not be used as an i/o pin. tosc1: timer oscillator pin 1. used only if internal calib rated rc oscillator is selected as chip clock source, and the asynchronous timer is ena bled by the correct se tting in assr. when the as2 bit in assr is set (one) to enable asynchronous clocking of timer/counter2, pin pb6 is di sconnected from the port, and becomes the input of the table 14-3. port b pins alternate functions port pin alternate functions pb7 xtal2 ( chip clock oscillator pin 2 ) tosc2 ( timer oscillator pin 2 ) pcint7 (pin change interrupt 7) pb6 xtal1 ( chip clock oscillator pin 1 or external clock input ) tosc1 ( timer oscillator pin 1 ) pcint6 (pin change interrupt 6) pb5 sck (spi bus master clock input) pcint5 (pin change interrupt 5) pb4 miso (spi bus master input/slave output) pcint4 (pin change interrupt 4) pb3 mosi (spi bus master output/slave input) oc2a (timer/counter2 output compare match a output) pcint3 (pin change interrupt 3) pb2 ss (spi bus master slave select) oc1b (timer/counter1 output compare match b output) pcint2 (pin change interrupt 2) pb1 oc1a (timer/counter1 output compare match a output) pcint1 (pin change interrupt 1) pb0 icp1 (timer/counter1 input capture input) clko (divided system clock output) pcint0 (pin change interrupt 0) 84 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 inverting oscillator amplifier. in this mode, a crystal osc illator is connected to this pi n, and the pin can not be used as an i/o pin. pcint6: pin change interrupt source 6. the pb6 pin can serve as an external interrupt source. if pb6 is used as a clock pin, ddb6, portb6 and pinb6 will all read 0. ? sck/pcint5 ? port b, bit 5 sck: master clock output, slave clock input pin for spi channel. when the spi is enable d as a slave, this pin is configured as an input regardless of the setting of ddb5. when the spi is enabled as a master, the data direction of this pin is controlled by ddb5. when the pin is forced by the spi to be an input, th e pull-up can still be controlled by the portb5 bit. pcint5: pin change interrupt source 5. the pb5 pin can serve as an external interrupt source. ? miso/pcint4 ? port b, bit 4 miso: master data input, slave data output pin for spi channel. when the spi is enabled as a master, this pin is configured as an input regardless of the setting of ddb4. wh en the spi is enabled as a slave, the data direction of this pin is controlled by ddb4. when the pin is forced by the spi to be an inpu t, the pull-up can still be controlled by the portb4 bit. pcint4: pin change interrupt source 4. the pb4 pin can serve as an external interrupt source. ? mosi/oc2/pcint3 ? port b, bit 3 mosi: spi master data output, slave data input for spi c hannel. when the spi is enable d as a slave, this pin is configured as an input regardless of the setting of ddb3. when the spi is enabled as a master, the data direction of this pin is controlled by ddb3. when the pin is forced by the spi to be an input, th e pull-up can still be controlled by the portb3 bit. oc2, output compare match output: the pb3 pin can serve as an external output for the timer/counter2 com- pare match. the pb3 pin has to be configured as an output (ddb3 set (one)) to serve this function. the oc2 pin is also the output pin for the pwm mode timer function. pcint3: pin change interrupt source 3. the pb3 pin can serve as an external interrupt source. ?ss /oc1b/pcint2 ? port b, bit 2 ss : slave select input. when the spi is enabled as a slave, this pin is configured as an input regardless of the set- ting of ddb2. as a slave, the spi is activated when this pi n is driven low. when the spi is enabled as a master, the data direction of this pin is controlled by ddb2. when the pi n is forced by the spi to be an input, the pull-up can still be controlled by the portb2 bit. oc1b, output compare match output: the pb2 pin can serv e as an external output for the timer/counter1 com- pare match b. the pb2 pin has to be configured as an out put (ddb2 set (one)) to serve this function. the oc1b pin is also the output pin for the pwm mode timer function. pcint2: pin change interrupt source 2. the pb2 pin can serve as an external interrupt source. ? oc1a/pcint1 ? port b, bit 1 oc1a, output compare match output: the pb1 pin can serv e as an external output for the timer/counter1 com- pare match a. the pb1 pin has to be configured as an out put (ddb1 set (one)) to serve this function. the oc1a pin is also the output pin for the pwm mode timer function. pcint1: pin change interrupt source 1. the pb1 pin can serve as an external interrupt source. ? icp1/clko/pcint0 ? port b, bit 0 icp1, input capture pin: the pb0 pin can act as an input capture pin for timer/counter1. 85 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 clko, divided system clock: the divided system clock can be output on the pb0 pin. the divided system clock will be output if the ckout fuse is pr ogrammed, regardless of the portb0 an d ddb0 settings. it will also be out- put during reset. pcint0: pin change interrupt source 0. the pb0 pin can serve as an external interrupt source. table 14-4 and table 14-5 on page 86 relate the alternate functions of port b to the overriding signals shown in figure 14-5 on page 81 . spi mstr input and spi slave output cons titute the miso si gnal, while mosi is divided into spi mstr output and spi slave input. notes: 1. intrc means that one of the in ternal rc oscillators are selected (by th e cksel fuses), extck means that exter- nal clock is selected (by the cksel fuses) table 14-4. overriding signals for alternate functions in pb7...pb4 signal name pb7/xtal2/ tosc2/pcint7 (1) pb6/xtal1/ tosc1/pcint6 (1) pb5/sck/ pcint5 pb4/miso/ pcint4 puoe intrc ? extck + as2 intrc + as2 spe ? mstr spe ? mstr puov 0 0 portb5 ? pud portb4 ? pud ddoe intrc ? extck + as2 intrc + as2 spe ? mstr spe ? mstr ddov0000 pvoe 0 0 spe ? mstr spe ? mstr pvov 0 0 sck output spi slave output dieoe intrc ? extck + as2 + pcint7 ? pcie0 intrc + as2 + pcint6 ? pcie0 pcint5 ? pcie0 pcint4 ? pcie0 dieov (intrc + extck) ? as2 intrc ? as2 11 di pcint7 input pcint6 input pcint5 input sck input pcint4 input spi mstr input aio oscillator output oscillator/clock input ?? 86 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 14.3.2 alternate functions of port c the port c pins with alternate functions are shown in table 14-6 . table 14-5. overriding signals for alternate functions in pb3...pb0 signal name pb3/mosi/ oc2/pcint3 pb2/ss / oc1b/pcint2 pb1/oc1a/ pcint1 pb0/icp1/ pcint0 puoe spe ? mstr spe ? mstr 00 puov portb3 ? pud portb2 ? pud 00 ddoe spe ? mstr spe ? mstr 00 ddov 0 0 0 0 pvoe spe ? mstr + oc2a enable oc1b enable oc1a enable 0 pvov spi mstr output + oc2a oc1b oc1a 0 dieoe pcint3 ? pcie0 pcint2 ? pcie 0 pcint1 ? pcie0 pcint0 ? pcie0 dieov 1 1 1 1 di pcint3 input spi slave input pcint2 input spi ss pcint1 input pcint0 input icp1 input aio ? ? ? ? table 14-6. port c pins alternate functions port pin alternate function pc6 reset (reset pin) pcint14 (pin change interrupt 14) pc5 adc5 (adc input channel 5) scl (2-wire serial bus clock line) pcint13 (pin change interrupt 13) pc4 adc4 (adc input channel 4) sda (2-wire serial bus data input/output line) pcint12 (pin change interrupt 12) pc3 adc3 (adc input channel 3) pcint11 (pin change interrupt 11) pc2 adc2 (adc input channel 2) pcint10 (pin change interrupt 10) pc1 adc1 (adc input channel 1) pcint9 (pin change interrupt 9) pc0 adc0 (adc input channel 0) pcint8 (pin change interrupt 8) 87 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 the alternate pin configuration is as follows: ? reset /pcint14 ? port c, bit 6 reset , reset pin: when the rstdisbl fuse is programmed, th is pin functions as a normal i/o pin, and the part will have to rely on power-on reset and brown-out reset as its reset source s. when the rstdisbl fuse is unpro- grammed, the reset circuitry is connected to the pin, and the pin can not be used as an i/o pin. if pc6 is used as a reset pin, ddc6, portc6 and pinc6 will all read 0. pcint14: pin change interrupt source 14. the pc6 pin can serve as an external interrupt source. ? scl/adc5/pcint13 ? port c, bit 5 scl, 2-wire serial interface clock: when the twen bit in twcr is set (one) to enable the 2-wire serial interface, pin pc5 is disconnected from the port and becomes the seri al clock i/o pin for the 2-wire serial interface. in this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. pc5 can also be used as adc input channel 5. no te that adc input channel 5 uses digital power. pcint13: pin change interrupt source 13. the pc5 pin can serve as an external interrupt source. ? sda/adc4/pcint12 ? port c, bit 4 sda, 2-wire serial interface data: when the twen bit in twcr is set (one) to enable the 2-wire serial interface, pin pc4 is disconnected from the port and becomes the serial data i/o pin for the 2-wire serial interface. in this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. pc4 can also be used as adc input channel 4. no te that adc input channel 4 uses digital power. pcint12: pin change interrupt source 12. the pc4 pin can serve as an external interrupt source. ? adc3/pcint11 ? port c, bit 3 pc3 can also be used as adc input channel 3. no te that adc input channel 3 uses analog power. pcint11: pin change interrupt source 11. the pc3 pin can serve as an external interrupt source. ? adc2/pcint10 ? port c, bit 2 pc2 can also be used as adc input channel 2. no te that adc input channel 2 uses analog power. pcint10: pin change interrupt source 10. the pc2 pin can serve as an external interrupt source. 88 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? adc1/pcint9 ? port c, bit 1 pc1 can also be used as adc input channel 1. no te that adc input channel 1 uses analog power. pcint9: pin change interrupt source 9. the pc1 pin can serve as an external interrupt source. ? adc0/pcint8 ? port c, bit 0 pc0 can also be used as adc input channel 0. no te that adc input channel 0 uses analog power. pcint8: pin change interrupt source 8. the pc0 pin can serve as an external interrupt source. table 14-7 and table 14-8 relate the alternate functions of port c to the overriding signals shown in figure 14-5 on page 81 . note: 1. when enabled, the 2-wire serial interface enables slew-r ate controls on the output pins pc4 and pc5. this is not shown in the figure. in addition, spike filters are connec ted between the aio outputs shown in the port figure and the digital logic of the twi module. table 14-7. overriding signals for alternate functions in pc6...pc4 (1) signal name pc6/reset /pcint14 pc5/scl/adc5/pci nt13 pc4/sda/adc4/pcint12 puoe rstdisbl twen twen puov 1 portc5 ? pud portc4 ? pud ddoe rstdisbl twen twen ddov 0 scl_out sda_out pvoe 0 twen twen pvov 0 0 0 dieoe rstdisbl + pcint14 ? pcie1 pcint13 ? pcie1 + adc5d p cint12 ? pcie1 + adc4d dieov rstdisbl pcint13 ? pcie1 pcint12 ? pcie1 di pcint14 input pcint13 input pcint12 input aio reset input adc5 input / scl input adc4 input / sda input 89 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 14.3.3 alternate functions of port d the port d pins with alternate functions are shown in table 14-9 . the alternate pin configuration is as follows: table 14-8. overriding signals for alternate functions in pc3...pc0 signal name pc3/adc3/ pcint11 pc2/adc2/ pcint10 pc1/adc1/ pcint9 pc0/adc0/ pcint8 puoe0000 puov0000 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe0000 pvov0000 dieoe pcint11 ? pcie1 + adc3d pcint10 ? pcie1 + adc2d pcint9 ? pcie1 + adc1d pcint8 ? pcie1 + adc0d dieov pcint11 ? pcie1 pcint10 ? pc ie1 pcint9 ? pcie1 pcint8 ? pcie1 di pcint11 input pcint10 input pcint9 input pcint8 input aio adc3 input adc2 input adc1 input adc0 input table 14-9. port d pins alternate functions port pin alternate function pd7 ain1 (analog comparator negative input) pcint23 (pin change interrupt 23) pd6 ain0 (analog comparator positive input) oc0a (timer/counter0 output compare match a output) pcint22 (pin change interrupt 22) pd5 t1 (timer/counter 1 ex ternal counter input) oc0b (timer/counter0 output compare match b output) pcint21 (pin change interrupt 21) pd4 xck (usart external clock input/output) t0 (timer/counter 0 ex ternal counter input) pcint20 (pin change interrupt 20) pd3 int1 (external interrupt 1 input) oc2b (timer/counter2 output compare match b output) pcint19 (pin change interrupt 19) pd2 int0 (external interrupt 0 input) pcint18 (pin change interrupt 18) pd1 txd (usart output pin) pcint17 (pin change interrupt 17) pd0 rxd (usart input pin) pcint16 (pin change interrupt 16) 90 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? ain1/oc2b/pcint23 ? port d, bit 7 ain1, analog comparator negative input. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interferin g with the function of the analog comparator. pcint23: pin change interrupt source 23. the pd7 pin can serve as an external interrupt source. ? ain0/oc0a/pcint22 ? port d, bit 6 ain0, analog comparator positive input. configure the por t pin as input with the internal pull-up switched off to avoid the digital port function from interferin g with the function of the analog comparator. oc0a, output compare match output: the pd6 pin can serv e as an external output for the timer/counter0 com- pare match a. the pd6 pin has to be configured as an output (ddd6 set (one)) to serve this function. the oc0a pin is also the output pin for the pwm mode timer function. pcint22: pin change interrupt source 22. the pd6 pin can serve as an external interrupt source. ? t1/oc0b/pcint21 ? port d, bit 5 t1, timer/counter1 counter source. oc0b, output compare match output: the pd5 pin can serv e as an external output for the timer/counter0 com- pare match b. the pd5 pin has to be configured as an output (ddd5 set (one)) to serve this function. the oc0b pin is also the output pin for the pwm mode timer function. pcint21: pin change interrupt source 21. the pd5 pin can serve as an external interrupt source. ? xck/t0/pcint20 ? port d, bit 4 xck, usart external clock. t0, timer/counter0 counter source. pcint20: pin change interrupt source 20. the pd4 pin can serve as an external interrupt source. ? int1/oc2b/pcint19 ? port d, bit 3 int1, external interrupt source 1: the pd3 pin can serve as an external interrupt source. oc2b, output compare match output: the pd3 pin can serv e as an external output for the timer/counter0 com- pare match b. the pd3 pin has to be configured as an output (ddd3 set (one)) to serve this function. the oc2b pin is also the output pin for the pwm mode timer function. pcint19: pin change interrupt source 19. the pd3 pin can serve as an external interrupt source. ? int0/pcint18 ? port d, bit 2 int0, external interrupt source 0: the pd2 pin can serve as an external interrupt source. pcint18: pin change interrupt source 18. the pd2 pin can serve as an external interrupt source. ? txd/pcint17 ? port d, bit 1 txd, transmit data (data output pin for the usart). when the usart transmitter is enabled, this pin is config- ured as an output regardless of the value of ddd1. pcint17: pin change interrupt source 17. the pd1 pin can serve as an external interrupt source. ? rxd/pcint16 ? port d, bit 0 rxd, receive data (data input pin for the usart). when th e usart receiver is enabled this pin is configured as an input regardless of the value of ddd0. when the usart forces this pin to be an input, the pull-up can still be controlled by the portd0 bit. 91 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 pcint16: pin change interrupt source 16. the pd0 pin can serve as an external interrupt source. table 14-10 and table 14-11 relate the alternate functions of port d to the overriding signals shown in figure 14-5 on page 81 . table 14-10. overriding signals for alternate functions pd7...pd4 signal name pd7/ain1 /pcint23 pd6/ain0/ oc0a/pcint22 pd5/t1/oc0b/ pcint21 pd4/xck/ t0/pcint20 puoe0000 puo0000 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe 0 oc0a enable oc0b enable umsel pvov 0 oc0a oc0b xck output dieoe pcint23 ? pcie2 pcint22 ? pcie 2 pcint21 ? pcie2 pcint20 ? pcie2 dieov1111 di pcint23 input pcint22 input pcint21 input t1 input pcint20 input xck input t0 input aio ain1 input ain0 input ? ? table 14-11. overriding signals for alternate functions in pd3...pd0 signal name pd3/oc2b/int1/ pcint19 pd2/int0/ pcint18 pd1/txd/ pcint17 pd0/rxd/ pcint16 puoe 0 0 txen rxen puo000portd0 ? pud ddoe 0 0 txen rxen ddov 0 0 1 0 pvoe oc2b enable 0 txen 0 pvov oc2b 0 txd 0 dieoe int1 enable + pcint19 ? pcie2 int0 enable + pcint18 ? pcie1 pcint17 ? pcie2 p cint16 ? pcie2 dieov1111 di pcint19 input int1 input pcint18 input int0 input pcint17 input pcint16 input rxd aio???? 92 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 14.4 register description 14.4.1 mcucr ? mcu control register notes: 1. bods and bodse only available for picopower devices atmega48pa/88pa/168pa/328p ? bit 4 ? pud: pull-up disable when this bit is written to one, the pull-ups in the i/o ports are disabled even if the ddxn and portxn registers are configured to enable the pull-ups ({ddxn, portxn} = 0b01). see ?configuring the pin? on page 77 for more details about this feature. 14.4.2 portb ? the port b data register 14.4.3 ddrb ? the port b data direction register 14.4.4 pinb ? the port b input pins address (1) 14.4.5 portc ? the port c data register 14.4.6 ddrc ? the port c data direction register 14.4.7 pinc ? the port c input pins address (1) bit 7 6 5 4 3 2 1 0 0x35 (0x55) ? bods (1) bodse (1) pud ? ? ivsel ivce mcucr read/write r r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x05 (0x25) portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x04 (0x24) ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x03 (0x23) pinb7 pinb6 pinb5 pinb4 pi nb3 pinb2 pinb1 pinb0 pinb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n /a n/a n/a n/a n/a n/a bit 76543210 0x08 (0x28) ? portc6 portc5 portc4 portc3 portc2 portc1 portc0 portc read/write r r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x07 (0x27) ? ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc read/write r r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x06 (0x26) ? pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 pinc read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 n/a n /a n/a n/a n/a n/a n/a 93 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 14.4.8 portd ? the port d data register 14.4.9 ddrd ? the port d data direction register 14.4.10 pind ? the port d input pins address (1) note: 1. writting to the pin register prov ides toggle functionality for io (see ?toggling the pin? on page 77 ) bit 76543210 0x0b (0x2b) portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 portd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x0a (0x2a) ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x09 (0x29) pind7 pind6 pind5 pind4 pi nd3 pind2 pind1 pind0 pind read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n /a n/a n/a n/a n/a n/a 94 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 15. 8-bit timer/counter0 with pwm 15.1 features ? two independent output compare units ? double buffered outp ut compare registers ? clear timer on compare match (auto reload) ? glitch free, phase correct pulse width modulator (pwm) ? variable pwm period ? frequency generator ? three independent interrupt sources (tov0, ocf0a, and ocf0b) 15.2 overview timer/counter0 is a general purpose 8-bit timer/counter module, with two independent output compare units, and with pwm support. it allows accurate program execution timing (event management) and wave generation. a simplified block diagram of the 8-bit timer/counter is shown in figure 15-1 . for the actual placement of i/o pins, refer to ?pinout atmega48a/pa/88a/pa/168a/pa/328/p? on page 2 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit locations are listed in the ?register description? on page 105 . the prtim0 bit in ?minimizing power consumption? on page 41 must be written to zero to enable timer/counter0 module. figure 15-1. 8-bit timer/counter block diagram clock select timer/counter data bus ocrna ocrnb = = tcntn waveform generation waveform generation ocna ocnb = fixed top value control logic = 0 top bottom count clear direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) tccrna tccrnb tn edge detector ( from prescaler ) clk tn 95 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 15.2.1 definitions many register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, in this case 0. a lower case ?x? replaces the output compare unit, in this case compare unit a or compare unit b. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt0 for accessing timer/counter0 counter value and so on. the definitions in table 15-1 are also used extensively throughout the document. table 15-1. definitions 15.2.2 registers the timer/counter (tcnt0) and output compare registers (ocr0a and ocr0b) are 8-bit registers. interrupt request (abbreviated to int.req. in the figure) signals are all visible in the timer interrupt flag register (tifr0). all interrupts are individually masked with the timer interr upt mask register (timsk0). tifr0 and timsk0 are not shown in the figure. the timer/counter can be clocked internally, via the prescale r, or by an external clock source on the t0 pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock sour ce is selected. the output fr om the clock select logic is referred to as the timer clock (clk t0 ). the double buffered output compare registers (ocr0a and ocr0b) are compared with the timer/counter value at all times. the result of the compare can be used by the waveform generator to generate a pwm or variable fre- quency output on the output compare pins (oc0a and oc0b). see ?using the output compare unit? on page 122 for details. the compare match event will also set the compare flag (ocf0a or ocf0b) which can be used to generate an output compare interrupt request. 15.3 timer/counter clock sources the timer/counter can be clocked by an internal or an ex ternal clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs02:0) bits located in the timer/counter control reg- ister (tccr0b). for de tails on clock sources and prescaler, see ?timer/counter0 and timer/counter1 prescalers? on page 139 . 15.4 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 15-2 shows a block diagram of the counter and its surroundings. bottom the counter reaches the bottom when it becomes 0x00. max the counter reaches its maximum when it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr0a register. the assignment is depen- dent on the mode of operation. 96 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 15-2. counter unit block diagram signal description (internal signals): count increment or decrement tcnt0 by 1. direction select between increment and decrement. clear clear tcnt0 (set a ll bits to zero). clk t n timer/counter clock, referred to as clk t0 in the following. top signalize that tcnt0 has reached maximum value. bottom signalize that tcnt0 has re ached minimum value (zero). depending of the mode of operation used, the counter is cl eared, incremented, or decremented at each timer clock (clk t0 ). clk t0 can be generated from an external or internal clock source, selected by the clock select bits (cs02:0). when no clock source is selected (cs02:0 = 0) the timer is stopped. however, the tcnt0 value can be accessed by the cpu, regardless of whether clk t0 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the wgm01 and wgm00 bits located in the timer/counter control register (tccr0a) and the wgm02 bit located in the timer/counter control register b (tccr0b). there are close connections between how t he counter behaves (counts) and how waveforms are generated on the out- put compare outputs oc0a and oc0b. for more deta ils about advanced counting sequences and waveform generation, see ?modes of operation? on page 99 . the timer/counter overflow flag (tov0) is set according to the mode of operation selected by the wgm02:0 bits. tov0 can be used for generating a cpu interrupt. 15.5 output compare unit the 8-bit comparator continuously compares tcnt0 with the output compare registers (ocr0a and ocr0b). whenever tcnt0 equals ocr0a or ocr0b, the comparator signals a match. a match will set the output com- pare flag (ocf0a or ocf0b) at the next timer clock cycle. if the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. the output compare flag is automatically cleared when the interrupt is executed. alternatively, the flag can be clea red by software by writing a lo gical one to its i/o bit loca- tion. the waveform generator uses the match signal to ge nerate an output according to operating mode set by the wgm02:0 bits and compare output mode (com0x1:0) bits. the max and bottom signals are used by the wave- form generator for handling the special cases of the extreme values in some modes of operation ( ?modes of operation? on page 99 ). figure 15-3 shows a block diagram of the output compare unit. data bus tcntn control logic count tovn (int.req.) clock select top tn edge detector ( from prescaler ) clk tn bottom direction clear 97 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 15-3. output compare unit, block diagram the ocr0x registers are double buffered when using an y of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buff- ering synchronizes the update of the ocr0x compare registers to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr0x register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocr0x buffer regi ster, and if double buffering is di sabled the cpu will access the ocr0x directly. 15.5.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (foc0x) bit. forcing compare match will not set the ocf0x flag or reload/clear the timer, but the oc0x pin will be updated as if a real compare match had occurred (the com0x1:0 bits settings define whether the oc0x pin is set, cleared or toggled). 15.5.2 compare match bloc king by tcnt0 write all cpu write operations to the tcnt0 register will block any compare matc h that occur in the next timer clock cycle, even when the timer is stopped. this feature allows ocr0x to be initialized to the same value as tcnt0 without triggering an interrupt when the timer/counter clock is enabled. 15.5.3 using the output compare unit since writing tcnt0 in any mode of operatio n will block all compare matches fo r one timer clock cycle, there are risks involved when changing tcnt0 when using the output compare unit, independently of whether the timer/counter is runnin g or not. if the value written to tcnt0 equals the ocr0x va lue, the compare match will be missed, resulting in incorrect waveform generation. sim ilarly, do not write the tcnt0 value equal to bottom when the counter is downcounting. the setup of the oc0x should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc0x value is to use the force output co mpare (foc0x) strobe bits in normal mode. the oc0x registers keep their values even when changing between waveform generation modes. ocfn x (int.req.) = (8-bit comparator ) ocrnx ocnx data b u s tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 98 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 be aware that the com0x1:0 bits are not double buffered together with the compare value. changing the com0x1:0 bits will take effect immediately. 15.6 compare match output unit the compare output mode (com0x1:0) bits have two f unctions. the waveform generator uses the com0x1:0 bits for defining the output compare (oc0x) state at the next compare match. also, the com0x1:0 bits control the oc0x pin output source. figure 15-4 shows a simplified schematic of the logic affected by the com0x1:0 bit set- ting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com0x1:0 bits are shown. when referring to the oc0x state, the reference is for the internal oc0x register, no t the oc0x pin. if a system reset occur, the oc0x register is reset to ?0?. figure 15-4. compare match output unit, schematic the general i/o port function is overridden by the outp ut compare (oc0x) from the waveform generator if either of the com0x1:0 bits are set. however, the oc0x pin direct ion (input or output) is still controlle d by the data direc- tion register (ddr) for the port pin. the data direction register bit for the oc0x pin (ddr_oc0x) must be set as output before the oc0x value is visible on the pin. th e port override function is independent of the waveform gen- eration mode. the design of the output compare pin logic allows initialization of the oc0x state before the output is enabled. note that some com0x1:0 bit settings are reserved for certain modes of operation. see ?register description? on page 105 . 15.6.1 compare output mode and waveform generation the waveform generator uses the com0x1:0 bits diff erently in normal, ctc, and pwm modes. for all modes, setting the com0x1:0 = 0 tells the waveform generator that no action on the oc0x register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 15-2 on page 105 . for fast pwm mode, refer to table 15-3 on page 105 , and for phase correct pwm refer to table 15-4 on page 106 . a change of the com0x1:0 bits state will have effect at the first compare match after the bi ts are writt en. for non- pwm modes, the action can be forced to have immediate effect by using the foc0x strobe bits. port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data bus focn clk i/o 99 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 15.7 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm02:0) and compare output mode (com0x1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com0x1:0 bits control whether the pwm output generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the com0x1:0 bits control whether the output should be set, cleared, or toggled at a compare match (see ?compare match output unit? on page 98 ). for detailed timing in formation refer to ?timer/counter timing diagrams? on page 103 . 15.7.1 normal mode the simplest mode of operation is the normal mode (wgm02 :0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 8- bit value (top = 0xff) and then restarts from the bott om (0x00). in normal operation the timer/counter overflow flag (tov0) will be set in the same ti mer clock cycle as the tcnt0 become s zero. the tov0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov0 flag, the timer reso lution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 15.7.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm02:0 = 2), the ocr0a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt0) matches the ocr0a. the ocr0a defines the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifie s the operation of counting external events. the timing diagram for the ctc mode is shown in figure 15-5 . the counter value (tcnt0 ) increases until a com- pare match occurs between tcnt0 and ocr0a, and then counter (tcnt0) is cleared. figure 15-5. ctc mode, timing diagram an interrupt can be generated each time the counter value reaches the top value by using the ocf0a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a value close to bottom when the counter is runni ng with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr0a is lower than the current value of tcnt0, the counter will miss the compare match. the count er will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, the oc0a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com0a1:0 = 1). the oc0a value will tcntn ocn (toggle) ocnx interrupt flag set 1 4 period 2 3 (comnx1:0 = 1) 100 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 not be visible on the port pin unless the data direction for the pin is set to output. the waveform generated will have a maximum frequency of f oc0 = f clk_i/o /2 when ocr0a is set to zero (0x00). the waveform frequency is defined by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tov0 flag is set in the same ti mer clock cycle that the counter counts from max to 0x00. 15.7.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm02:0 = 3 or 7) provides a high frequency pwm wave- form generation option. the fast pwm differs from the other pwm option by its single-slope operation. the counter counts from bottom to top then restarts from bottom. top is defined as 0xff when wgm2:0 = 3, and ocr0a when wgm2:0 = 7. in non-inverting compare output mode, the output compare (oc0x) is cleared on the compare match between tcnt0 and ocr0x, and set at bottom. in inverting compare output mode, the output is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase correct pwm mode that use dual-slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac applications. high frequency allows physically small siz ed external components (coils, capacitors), and therefore reduces total sys- tem cost. in fast pwm mode, the counter is incremented until the counter value matches the top value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 15-6 . the tcnt0 value is in the timing diagram shown as a histogram for illustrating the single-slope op eration. the diagram includes non-inverted and inverted pwm outputs. the sma ll horizontal line marks on the tcnt0 slopes represent compare matches between ocr0x and tcnt0. figure 15-6. fast pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches top. if the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. in fast pwm mode, the compare unit allows generation of pwm waveforms on the oc0x pins. setting the com0x1:0 bits to two will produce a non-inverted pwm and an inverted pwm ou tput can be gener ated by setting the com0x1:0 to three: setting the com0a1:0 bits to one allows the oc0a pin to toggle on compare matches if f ocnx f clk_i/o 2 n 1 ocrnx + ?? ?? ------------------------------------------------- - = tcntn ocrnx update and tovn interrupt flag set 1 period 2 3 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag set 4 5 6 7 101 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 the wgm02 bit is set. this option is not available for the oc0b pin (see table 15-6 on page 106 ). the actual oc0x value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm waveform is generated by setting (or clearing) the oc0x register at the compare match between ocr0x and tcnt0, and clearing (or setting) the oc0x register at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represents s pecial cases when generating a pwm waveform output in the fast pwm mode. if the ocr0a is set equal to bottom, the ou tput will be a narrow spike for each max+1 timer clock cycle. setting the ocr0a equal to max will resu lt in a constantly high or low output (depending on the polarity of the output set by the com0a1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast pwm mode can be achieved by setting oc0x to toggle its logical level on each compare match (com0x1:0 = 1). the waveform generated will have a maximum frequency of f oc0 = f clk_i/o /2 when ocr0a is set to zero. this feature is similar to the oc0a toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast pwm mode. 15.7.4 phase correct pwm mode the phase correct pwm mode (wgm02:0 = 1 or 5) provides a high resolution phase correct pwm waveform gen- eration option. the phase correct pwm mode is based on a dual-slope operation. the counter counts repeatedly from bottom to top and then from top to bottom. top is defined as 0xff when wgm2:0 = 1, and ocr0a when wgm2:0 = 5. in non-inverting compare output mode, the output compare (oc0x) is cleared on the com- pare match between tcnt0 and ocr0x while upcounting, and set on the compare match while downcounting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. in phase correct pwm mode the counter is incremented unt il the counter value matches top. when the counter reaches top, it change s the count direction. the tcnt0 value will be eq ual to top for one ti mer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 15-7 . the tcnt0 value is in the timing dia- gram shown as a histogram for illu strating the dua l-slope operatio n. the diagram incl udes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent compare matches between ocr0x and tcnt0. f ocnxpwm f clk_i/o n 256 ? ------------------ = 102 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 15-7. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each ti me the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct pwm mode, the compare unit allows generation of pwm waveforms on the oc0x pins. setting the com0x1:0 bits to two will produce a non-inverted pwm. an inverted pwm output can be generated by setting the com0x1:0 to three: setting the com0a0 bits to one allows the oc0a pin to toggle on compare matches if the wgm02 bit is set. this option is not available for the oc0b pin (see table 15-7 on page 107 ). the actual oc0x value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm waveform is generated by clearing (or setting) the oc0x register at the compare match between ocr0x and tcnt0 when the counter increments, and setting (or clearing) the oc0x register at compare match between ocr0x and tcnt0 when the counter decrements. the pwm frequency for t he output when using phase correct pwm can be calcu- lated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the o cr0a is set equal to bottom, the outp ut will be continuously low and if set equal to max the output will be continuously high for non-inverted pwm mode. for inverted pwm the output will have the opposite logic values. at the very start of period 2 in figure 15-7 ocnx has a transition from high to low even though there is no compare match. the point of this transition is to guarantee symmetry around bottom. there are two cases that give a transition without compare match. ? ocrnx changes its valu e from max, like in figure 15-7 . when the ocr0a value is max the ocn pin value is the same as the result of a down-counting compare match. to ensure symmetry around bottom the ocnx value at max must correspond to the result of an up-counting compare match. ? the timer starts counting from a value higher than the one in ocrnx, and for that reason misses the compare match and hence the ocnx change that would have happened on the way up. tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx update f ocnxpcpwm f clk_i/o n 510 ? ------------------ = 103 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 15.8 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t0 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set. figure 15-8 contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max value in all modes other than phase correct pwm mode. figure 15-8. timer/counter timing diagram, no prescaling figure 15-9 shows the same timing data, but with the prescaler enabled. figure 15-9. timer/counter timing dia gram, with prescaler (f clk_i/o /8) figure 15-10 shows the setting of ocf0b in all modes and ocf0a in all modes except ctc mode and pwm mode, where ocr0a is top. figure 15-10. timer/counter timing diagram, setting of ocf0x, with prescaler (f clk_i/o /8) figure 15-11 shows the setting of ocf0a and the clearing of tcnt0 in ctc mode and fast pwm mode where ocr0a is top. clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) 104 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 15-11. timer/counter timing diagram, clear timer on compare match mode, with prescaler (f clk_i/o /8) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) 105 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 15.9 register description 15.9.1 tccr0a ? timer/counter control register a ? bits 7:6 ? com0a1:0: compare match output a mode these bits control the output compare pin (oc0a) behavior. if one or both of the com0a1:0 bits are set, the oc0a output overrides the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corresponding to the oc0a pin must be set in order to enable the output driver. when oc0a is connected to the pin, the function of the com0a1:0 bits depends on the wgm02:0 bit setting. table 15-2 shows the com0a1:0 bit functionality when the wgm02:0 bits are set to a normal or ctc mode (non- pwm). table 15-3 shows the com0a1:0 bit functionality when the wgm01:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr0a equals top and com0 a1 is set. in this case, the compare match is ignored, but the set or clear is done at bottom. see ?fast pwm mode? on page 100 for more details. table 15-4 shows the com0a1:0 bit functionality when the wgm02:0 bits are set to phase correct pwm mode. bit 7 6 5 4 3 2 1 0 0x24 (0x44) com0a1 com0a0 com0b1 com0b0 ? ? wgm01 wgm00 tccr0a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 15-2. compare output mode, non-pwm mode com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 toggle oc0a on compare match 1 0 clear oc0a on compare match 1 1 set oc0a on compare match table 15-3. compare output mode, fast pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01 wgm02 = 0: normal port operation, oc0a disconnected. wgm02 = 1: toggle oc0a on compare match. 10 clear oc0a on compare match, set oc0a at bottom, (non-inverting mode). 11 set oc0a on compare match, clear oc0a at bottom, (inverting mode). 106 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. a special case occurs when ocr0a equals top and com0 a1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 126 for more details. ? bits 5:4 ? com0b1:0: compare match output b mode these bits control the output compare pin (oc0b) behavior. if one or both of the com0b1:0 bits are set, the oc0b output overrides the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corresponding to the oc0b pin must be set in order to enable the output driver. when oc0b is connected to the pin, the function of the com0b1:0 bits depends on the wgm02:0 bit setting. table 15-5 shows the com0b1:0 bit functionality when the wgm02:0 bits are set to a normal or ctc mode (non- pwm). table 15-6 shows the com0b1:0 bit functionality when the wgm02:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr0b equals top and com0 b1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 100 for more details. table 15-7 shows the com0b1:0 bit functionality when the wgm02:0 bits are set to phase correct pwm mode. table 15-4. compare output mode, phase correct pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01 wgm02 = 0: normal port o peration, oc0a disconnected. wgm02 = 1: toggle oc0a on compare match. 10 clear oc0a on compare match when up-counting. set oc0a on compare match when down-counting. 11 set oc0a on compare match when up-counting. clear oc0a on compare match when down-counting. table 15-5. compare output mode, non-pwm mode com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 0 1 toggle oc0b on compare match 1 0 clear oc0b on compare match 1 1 set oc0b on compare match table 15-6. compare output mode, fast pwm mode (1) com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 01reserved 10 clear oc0b on compare match, set oc0b at bottom, (non-inverting mode) 11 set oc0b on compare match, clear oc0b at bottom, (inverting mode). 107 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. a special case occurs when ocr0b equals top and com0 b1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 101 for more details. ? bits 3, 2 ? reserved these bits are reserved bits in the atmega48a/pa/88a/pa/168a/pa/32 8/p and will always read as zero. ? bits 1:0 ? wgm01:0: waveform generation mode combined with the wgm02 bit found in the tccr0b regist er, these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of waveform generation to be used, see table 15-8 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes (see ?modes of operation? on page 99 ). notes: 1. max = 0xff 2. bottom = 0x00 table 15-7. compare output mode, phase correct pwm mode (1) com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 01reserved 10 clear oc0b on compare match when up-counting. set oc0b on compare match when down-counting. 11 set oc0b on compare match when up-counting. clear oc0b on compare match when down-counting. table 15-8. waveform generation mode bit description mode wgm02 wgm01 wgm00 timer/counter mode of operation top update of ocrx at tov flag set on (1)(2) 0 0 0 0 normal 0xff immediate max 10 0 1 pwm, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 3 0 1 1 fast pwm 0xff bottom max 4 1 0 0 reserved ? ? ? 51 0 1 pwm, phase correct ocra top bottom 6 1 1 0 reserved ? ? ? 7 1 1 1 fast pwm ocra bottom top 108 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 15.9.2 tccr0b ? timer/counter control register b ? bit 7 ? foc0a: force output compare a the foc0a bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring co mpatibility with future devices, this bit must be set to zero when tccr0b is written when operating in pwm mode. when writing a logical one to the foc0a bit, an immediate compare match is forced on the waveform generation unit. the oc0a output is changed according to its com0a1:0 bits setting. note that the foc0a bit is implemented as a strobe. therefore it is the value present in the com0a1:0 bits that determines the effect of the forced compare. a foc0a strobe will not generate any interrupt, nor will it clear the time r in ctc mode using ocr0a as top. the foc0a bit is always read as zero. ? bit 6 ? foc0b: force output compare b the foc0b bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring co mpatibility with future devices, this bit must be set to zero when tccr0b is written when operating in pwm mode. when writing a logical one to the foc0b bit, an immediate compare match is forced on the waveform generation unit. the oc0b output is changed according to its com0b1:0 bits setting. note that the foc0b bit is implemented as a strobe. therefore it is the value present in the com0b1:0 bits that determines the effect of the forced compare. a foc0b strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr0b as top. the foc0b bit is always read as zero. ? bits 5:4 ? reserved these bits are reserved bits in the atmega48a/pa/88a/pa/168a/pa/32 8/p and will always read as zero. ? bit 3 ? wgm02: waveform generation mode see the description in the ?tccr0a ? timer/counter contro l register a? on page 105 . ? bits 2:0 ? cs02:0: clock select the three clock select bits select the clock source to be used by the timer/counter. bit 7 6 5 4 3 2 1 0 0x25 (0x45) foc0a foc0b ? ? wgm02 cs02 cs01 cs00 tccr0b read/write w w r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 109 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 if external pin modes are used for the timer/counter0, transitions on the t0 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 15.9.3 tcnt0 ? timer/counter register the timer/counter register gives direct access, both for re ad and write operations, to the timer/counter unit 8-bit counter. writing to the tcnt0 register blocks (removes) the compare match on the following timer clock. modify- ing the counter (tcnt0) while the counter is running, introduces a risk of missing a compare match between tcnt0 and the ocr0x registers. 15.9.4 ocr0a ? output compare register a the output compare register a contains an 8-bit value that is continuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0a pin. 15.9.5 ocr0b ? output compare register b the output compare register b contains an 8-bit value that is continuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0b pin. table 15-9. clock select bit description cs02 cs01 cs00 description 0 0 0 no clock source (timer/counter stopped) 001clk i/o /(no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t0 pin. clock on falling edge. 1 1 1 external clock source on t0 pin. clock on rising edge. bit 76543210 0x26 (0x46) tcnt0[7:0] tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x27 (0x47) ocr0a[7:0] ocr0a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x28 (0x48) ocr0b[7:0] ocr0b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 110 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 15.9.6 timsk0 ? timer/counter interrupt mask register ? bits 7:3 ? reserved these bits are reserved bits in the atmega48a/pa/88a/pa/168a/pa/32 8/p and will always read as zero. ? bit 2 ? ocie0b: timer/counter output compare match b interrupt enable when the ocie0b bit is written to one, and the i-bit in the status register is set, the timer/counter compare match b interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter occurs, i.e., when the ocf0b bit is set in the timer/counter interrupt flag register ? tifr0. ? bit 1 ? ocie0a: timer/counter0 output compare match a interrupt enable when the ocie0a bit is written to one, and the i-bit in the status register is set, the timer/counter0 compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter0 occurs, i.e., when the ocf0a bit is set in the timer/counter 0 interrupt flag register ? tifr0. ? bit 0 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is written to one, and the i-bit in the status register is set, the timer/counter0 overflow inter- rupt is enabled. the corresponding interrupt is executed if an overflow in timer/counter0 occurs, i.e., when the tov0 bit is set in the timer/counter 0 interrupt flag register ? tifr0. 15.9.7 tifr0 ? timer/counter 0 interrupt flag register ? bits 7:3 ? reserved these bits are reserved bits in the atmega48a/pa/88a/pa/168a/pa/32 8/p and will always read as zero. ? bit 2 ? ocf0b: timer/counter 0 output compare b match flag the ocf0b bit is set when a compare match occurs betw een the timer/counter and the data in ocr0b ? output compare register0 b. ocf0b is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf0b is cleared by wr iting a logic one to the flag. when the i-bit in sreg, ocie0b (timer/counter compare b match interrupt enable), and ocf0b are set, the timer/counter compare match interrupt is executed. ? bit 1 ? ocf0a: timer/counter 0 output compare a match flag the ocf0a bit is set when a compare match occurs between the timer/counter0 and the data in ocr0a ? out- put compare register0. ocf0a is cleared by hardwar e when executing the corresponding interrupt handling vector. alternatively, ocf0a is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0a (timer/counter0 compare match interrupt enable), and ocf0a are set, the timer/counter0 compare match inter- rupt is executed. ? bit 0 ? tov0: timer/counter0 overflow flag the bit tov0 is set when an overflow occurs in timer/co unter0. tov0 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov0 is cleared by writing a logic one to the flag. when the bit 7 6 5 4 3 2 1 0 (0x6e) ? ? ? ? ? ocie0b ocie0a toie0 timsk0 read/write rrrrrr/wr/wr/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x15 (0x35) ?????ocf0bocf0atov0tifr0 read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 111 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 sreg i-bit, toie0 (timer/counter0 overflow interrupt enable), and tov0 are set, the timer/counter0 overflow interrupt is executed. the setting of this flag is dependent of the wgm02:0 bit setting. refer to table 15-8 , ?waveform generation mode bit description? on page 107 . 112 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 16. 16-bit timer/counter1 with pwm 16.1 features ? true 16-bit design (i.e., allows 16-bit pwm) ? two independent output compare units ? double buffered outp ut compare registers ? one input capture unit ? input capture noise canceler ? clear timer on compare match (auto reload) ? glitch-free, phase correct pu lse width modulator (pwm) ? variable pwm period ? frequency generator ? external event counter ? four independent interrupt sources (tov1, ocf1a, ocf1b, and icf1) 16.2 overview the 16-bit timer/counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. most register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, and a lower case ?x? replaces the output compare unit channel. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt1 for accessing timer/counter1 counter value and so on. a simplified block diagram of the 16-bit timer/counter is shown in figure 16-1 . for the actual placement of i/o pins, refer to ?pinout atmega48a/pa/88a/pa/168a/pa/328/p? on page 2 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-spe cific i/o register and bit locations are listed in the ?register description? on page 132 . the prtim1 bit in ?prr ? power reduction register? on page 44 must be written to zero to enable timer/counter1 module. 113 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 16-1. 16-bit timer/counter block diagram (1) note: 1. refer to figure 1-1 on page 2 , table 14-3 on page 83 and table 14-9 on page 89 for timer/counter1 pin placement and description. 16.2.1 registers the timer/counter (tcnt1), output compare registers (ocr1a/b), and input capture register (icr1) are all 16-bit registers. special procedures must be followed w hen accessing the 16-bit registers. these procedures are described in the section ?accessing 16-bit registers? on page 114 . the timer/counter control registers (tccr1a/b) are 8-bit registers and have no cpu access rest rictions. interrupt requests (abbreviated to int.req. in the figure) signals are all visible in the timer interrupt flag register (tifr1). all interrupts are individually masked with the timer interrupt mask register (timsk1). tifr1 and timsk1 are not shown in the figure. the timer/counter can be clocked internally, via the prescale r, or by an external clock source on the t1 pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock sour ce is selected. the output fr om the clock select logic is referred to as the timer clock (clk t 1 ). the double buffered output compare registers (ocr1a/b) are compared with the timer/counter value at all time. the result of the compare can be used by the waveform generator to generate a pwm or variable frequency out- put on the output compare pin (oc1a/b). see ?output compare units? on page 120 . the compare match event will also set the compare match flag (ocf1a/b) which can be used to generate an output compare interrupt request. clock select timer/counter data b u s ocrna ocrnb icrn = = tcntn waveform generation waveform generation ocna ocnb noise canceler icpn = fixed top values edge detector control logic = 0 top bottom count clear direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) icfn (int.req.) tccrna tccrnb ( from analog comparator ouput ) tn edge detector ( from prescaler ) clk tn 114 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 the input capture register can capture the timer/count er value at a given external (edge triggered) event on either the input capture pin (icp1) or on the analog comparator pins (see ?analog comparator? on page 239 ) the input capture unit includes a digital filtering unit (noi se canceler) for reducing the chance of capturing noise spikes. the top value, or maximum timer/counter value, can in some modes of operation be defined by either the ocr1a register, the icr1 register, or by a set of fixed values. when using ocr1 a as top value in a pwm mode, the ocr1a register can not be used for generating a pwm output. however, the top value will in this case be double buffered allowing the top value to be changed in run time. if a fixed top value is required, the icr1 register can be used as an alternative, freeing the ocr1a to be used as pwm output. 16.2.2 definitions the following definitions are used extensively throughout the section: 16.3 accessing 16-bit registers the tcnt1, ocr1a/b, and icr1 are 16-bit registers that can be accessed by the avr cpu via the 8-bit data bus. the 16-bit register must be byte accessed using two read or write operations. each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. the same temporary register is shared between all 16-bit registers within each 16-bit timer. accessing the low byte triggers the 16-bit read or write operation. when the low byte of a 16-bit register is written by the cpu, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. when the low byte of a 16-bit register is read by the cpu, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. not all 16-bit accesses uses the temporary register fo r the high byte. reading the ocr1a/b 16-bit registers does not involve using the temporary register. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before the high byte. the following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. the same principle can be used directly for accessing the ocr1a/b and icr1 registers. note that when using ?c?, the compiler handles the 16-bit access. bottom the counter reaches the bottom when it becomes 0x0000. max the counter reaches its max imum when it becomes 0xffff (decimal 65535). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be one of the fixed values: 0x00ff, 0x01ff, or 0x03ff, or to the value stored in the o cr1a or icr1 register. the assignment is dependent of the mode of operation. 115 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. see ?about code examples? on page 7. for i/o registers located in extended i/ o map, ?in?, ?out?, ?sbis?, ?sbic?, ?c bi?, and ?sbi? instructions must be replaced with instructions that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example returns the tcnt1 value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers are atomic operations. if an interrupt occurs between the two instructions accessing the 16-bit register, and the interr upt code updates the temporary register by accessing the same or any other of th e 16-bit timer registers, then the result of the access outsid e the interrupt will be corrupted. therefore, when both the main code and the interrupt code update the temporary register, the main code must dis- able the interrupts during the 16-bit access. the following code examples show how to do an atomic read of the tcnt1 register contents. reading any of the ocr1a/b or icr1 registers can be done by using the same principle. assembly code examples (1) ... ; set tcnt 1 to 0x01ff ldi r17,0x01 ldi r16,0xff out tcnt 1 h,r17 out tcnt 1 l,r16 ; read tcnt 1 into r17:r16 in r16,tcnt 1 l in r17,tcnt 1 h ... c code examples (1) unsigned int i; ... /* set tcnt 1 to 0x01ff */ tcnt 1 = 0x1ff; /* read tcnt 1 into i */ i = tcnt 1 ; ... 116 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. see ?about code examples? on page 7. for i/o registers located in extended i/ o map, ?in?, ?out?, ?sbis?, ?sbic?, ?c bi?, and ?sbi? instructions must be replaced with instructions that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example returns the tcnt1 value in the r17:r16 register pair. the following code examples show how to do an atomic wr ite of the tcnt1 register contents. writing any of the ocr1a/b or icr1 registers can be done by using the same principle. assembly code example (1) tim16_readtcnt 1 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcnt 1 into r17:r16 in r16,tcnt 1 l in r17,tcnt 1 h ; restore global interrupt flag out sreg,r18 ret c code example (1) unsigned int tim16_readtcnt 1 ( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* read tcnt 1 into i */ i = tcnt 1 ; /* restore global interrupt flag */ sreg = sreg; return i; } 117 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. see ?about code examples? on page 7. for i/o registers located in extended i/ o map, ?in?, ?out?, ?sbis?, ?sbic?, ?c bi?, and ?sbi? instructions must be replaced with instructions that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example requires that the r17:r16 register pair contains the value to be written to tcnt1. 16.3.1 reusing the temporary high byte register if writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. however, note that the same rule of atomic operation described previously also applies in this case. 16.4 timer/counter clock sources the timer/counter can be clocked by an internal or an ex ternal clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs12:0) bits located in the timer/counter control regis- ter b (tccr1b). for details on clock sources and prescaler, see ?timer/counter0 and timer/counter1 prescalers? on page 139 . assembly code example (1) tim16_writetcnt 1 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcnt 1 to r17:r16 out tcnt 1 h,r17 out tcnt 1 l,r16 ; restore global interrupt flag out sreg,r18 ret c code example (1) void tim16_writetcnt 1 ( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* set tcnt 1 to i */ tcnt 1 = i; /* restore global interrupt flag */ sreg = sreg; } 118 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 16.5 counter unit the main part of the 16-bit timer/counter is the programmable 16-bit bi-directional counter unit. figure 16-2 shows a block diagram of the counter and its surroundings. figure 16-2. counter unit block diagram signal description (internal signals): count increment or decrement tcnt1 by 1. direction select between increment and decrement. clear clear tcnt1 (set a ll bits to zero). clk t 1 timer/counter clock. top signalize that tcnt1 has reached maximum value. bottom signalize that tcnt1 has re ached minimum value (zero). the 16-bit counter is mapped into two 8-bit i/o memory locations: counter high (tcnt1h) containing the upper eight bits of the counter, and counter low (tcnt1l) containing the lower eight bits. the tcnt1h register can only be indirectly accessed by the cp u. when the cpu does an access to the tcnt1h i/o location, the cpu accesses the high byte temporary register (temp). the temporary register is updated with the tcnt1h value when the tcnt1l is read, and tcnt1h is updated with the temporary register value when tcnt1l is written. this allows the cpu to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. it is important to notice that there are special cases of writing to the tcnt1 register when the counter is counting that will give unpredictable results. the special cases are descr ibed in the sections wher e they are of importance. depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t 1 ). the clk t 1 can be generated from an external or internal clock source, selected by the clock select bits (cs12:0). when no clock source is selected (cs12:0 = 0) the timer is stopped. however, the tcnt1 value can be accessed by the cpu, independent of whether clk t 1 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the waveform generation mode bits (wgm13:0) located in the timer/counter control registers a and b (tccr1a and tccr1b). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs oc1x. for more details about advanced counting seque nces and waveform generation, see ?modes of operation? on page 123 . the timer/counter overflow flag (tov1) is set according to the mode of operation selected by the wgm13:0 bits. tov1 can be used for generating a cpu interrupt. 16.6 input capture unit the timer/counter incorporates an input capture unit that can capture external events and give them a time- stamp indicating time of occurrence. the external signal indicating an event, or multiple events, can be applied via temp (8-bit) data bus (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) control logic count clear direction tovn (int.req.) clock select top bottom tn edge detector ( from prescaler ) clk tn 119 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 the icp1 pin or alternatively, via the analog-comparator unit. the time-stamps can then be used to calculate fre- quency, duty-cycle, and other features of the signal app lied. alternatively the time-stamps can be used for creating a log of the events. the input capture unit is illustrated by the block diagram shown in figure 16-3 . the elements of the block diagram that are not directly a part of the input capture unit are gray shaded. the small ?n? in register and bit names indi- cates the timer/counter number. figure 16-3. input capture unit block diagram when a change of the logic level (an event) occurs on the input capture pin (icp1), alternatively on the analog comparator output (aco), and this change confirms to the setting of the edge det ector, a capture will be triggered. when a capture is triggered, the 16-bit value of the counter (tcnt1) is written to the input capture register (icr1). the input capture flag (icf1) is set at the same system clock as the tcnt1 value is copied into icr1 register. if enabled (icie1 = 1), the input capture flag generates an input capture interrupt. the icf1 flag is automatically cleared when the interrupt is executed. al ternatively the icf1 flag can be cleared by software by writing a logical one to its i/o bit location. reading the 16-bit value in the input capture register (icr1) is done by first reading the low byte (icr1l) and then the high byte (icr1h). when the low byte is read the high byte is copied into the high byte temporary register (temp). when the cpu reads th e icr1h i/o location it will access the temp register. the icr1 register can only be written when using a waveform generation mode that utilizes the icr1 register for defining the counter?s top value. in th ese cases the waveform generation mode (wgm13:0) bits must be set before the top value can be written to the icr1 register. when writing the icr1 register the high byte must be written to the icr1h i/o location before the low byte is written to icr1l. for more information on how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 114 . 16.6.1 input capture trigger source the main trigger source for the input capture unit is the input capture pin (icp1). timer/counter1 can alternatively use the analog comparator output as trigger source for the input capture unit. the analog comparator is selected as trigger source by setting the analog comparator input capture (acic) bit in the analog comparator control and icfn (int.req.) analog comparator write icrn (16-bit register) icrnh (8-bit) noise canceler icpn edge detector temp (8-bit) data bus (8-bit) icrnl (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) acic* icnc ices aco* 120 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 status register (acsr). be aware that changing trigger source can trigger a capture. the input capture flag must therefore be cleared after the change. both the input capture pin (icp1) and the analog comparator output (aco) inputs are sampled using the same technique as for the t1 pin ( figure 17-1 on page 139 ). the edge detector is also identical. howe ver, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. note that the input of the noise canceler and edge detector is always enabled unless the timer/counter is set in a waveform generation mode that uses icr1 to define top. an input capture can be trigger ed by software by controlling the port of the icp1 pin. 16.6.2 noise canceler the noise canceler improves noise immunity by using a si mple digital filtering scheme. the noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the input capture noise canceler (icnc1) bit in timer/counter control register b (tccr1b). when enabled the noise canceler introduc es additional four system clock cycles of delay from a change applied to the input, to the update of th e icr1 register. the noise canceler uses the system clock and is therefore not affected by the prescaler. 16.6.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processo r capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured value in the icr1 register before the next event o ccurs, the icr1 will be overwritten with a ne w value. in this case the result of the capture will be incorrect. when using the input capture interrupt, the icr1 register should be read as early in the interrupt handler routine as possible. even though the input capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. using the input capture unit in any mode of operation when the top value (resolution) is actively changed during operation, is not recommended. measurement of an external signal?s duty cycle requires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as po ssible after the icr1 register has been read. after a change of the edge, the input capture flag (icf1) must be cleared by software (writing a logical one to the i/o bit location). for measuring frequency only, the clearing of th e icf1 flag is not required (if an interrupt handler is used). 16.7 output compare units the 16-bit comparator continuously compares tcnt1 with the output compare register (ocr1x). if tcnt equals ocr1x the comparator signals a match. a match will set the output compare flag (ocf1x) at the next timer clock cycle . if enabled (ocie1x = 1), the output compare flag generates an output compare interrupt. the ocf1x flag is automatically cleared when the interrupt is executed. alternatively the ocf1x flag can be cleared by software by writing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operating mode set by the waveform generation mode (wgm13:0) bits and compare output mode (com1x1:0) bits. the top and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation ( see section ?16.9? on page 123. ) a special feature of output compare unit a allows it to define the timer/counter top value (i.e., counter resolu- tion). in addition to the counter resolution, the top value defines the period time for waveforms generated by the waveform generator. 121 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 16-4 shows a block diagram of the output compare unit. the small ?n? in the register and bit names indi- cates the device number (n = 1 for timer/counter 1), and the ?x? indicates output compare unit (a/b). the elements of the block diagram that are not directly a part of the output compare unit are gray shaded. figure 16-4. output compare unit, block diagram the ocr1x register is double buffered when using any of the twelve pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocr1x compare register to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr1x register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocr1x buffer regi ster, and if double buffering is di sabled the cpu will access the ocr1x directly. the content of the ocr1x (buffer or compare) register is only changed by a write operation (the timer/counter does not update this register automatically as the tcnt1 and icr1 register). therefore ocr1x is not read via the high byte temporary register (temp). however, it is a good practice to read the low byte first as when accessing other 16-bit registers. writing the ocr1x registers must be done via the temp register since the compare of all 16 bits is done continuously. the high byte (ocr1xh) has to be written first. when the high byte i/o location is written by the cpu, the temp register will be updated by the value written. then when the low byte (ocr1xl) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the ocr1x buffer or ocr1x compare register in the same system clock cycle. for more information of how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 114 . 16.7.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (foc1x) bit. forcing compare match will not set the ocf1x flag or reload/clear the timer, but the oc1x pin will be updated as if a real com pare match had occurred (the com11:0 bits settings define whether the oc1x pin is set, cleared or toggled). ocfnx (int.req.) = (16-bit comparator ) ocrnx buffer (16-bit register) ocrnxh buf. (8-bit) ocnx temp (8-bit) data bus (8-bit) ocrnxl buf. (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) comnx1:0 wgmn3:0 ocrnx (16-bit register) ocrnxh (8-bit) ocrnxl (8-bit) waveform generator top bottom 122 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 16.7.2 compare match bloc king by tcnt1 write all cpu writes to the tcnt1 register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocr1x to be initialized to the same va lue as tcnt1 without trigger- ing an interrupt when the timer/counter clock is enabled. 16.7.3 using the output compare unit since writing tcnt1 in any mode of operatio n will block all compare matches fo r one timer clock cycle, there are risks involved when changing tcnt1 when using any of the output compare channels, independent of whether the timer/counter is running or not. if the value written to tcnt1 e quals the ocr1x value, the compare match will be missed, resulting in incorrect waveform generation. do not write the tcnt1 equal to top in pwm modes with variable top values. the compare match for the top will be ignored and the counter will continue to 0xffff. similarly, do not write the tcnt1 value equal to bottom when the counter is downcounting. the setup of the oc1x should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc1x value is to use the force output co mpare (foc1x) strobe bits in normal mode. the oc1x register keeps its value even wh en changing between waveform generation modes. be aware that the com1x1:0 bits are not double buffered together with the compare value. changing the com1x1:0 bits will take effect immediately. 16.8 compare match output unit the compare output mode (com1x1:0) bits have two functions. the waveform generator uses the com1x1:0 bits for defining the output compare (oc1x) state at the next compare match. secondly the com1x1:0 bits control the oc1x pin output source. figure 16-5 shows a simplified schematic of the logic affected by the com1x1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the fi gure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com1x1:0 bits are shown. when referring to the oc1x state, the reference is for the internal oc1x regi ster, not the oc1x pin. if a system reset occur, the oc1x register is reset to ?0?. figure 16-5. compare match output unit, schematic port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data b u s focnx clk i/o 123 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 the general i/o port function is overridden by the outp ut compare (oc1x) from the waveform generator if either of the com1x1:0 bits are set. howe ver, the oc1x pin direction (input or output) is still controlled by the data direc- tion register (ddr) for the port pin. the data direction register bit for the oc 1x pin (ddr_oc1x) must be set as output before the oc1x value is visible on the pin. the port override function is generally independent of the wave- form generation mode, but there are some exceptions. refer to table 16-1 on page 132 , table 16-2 on page 132 and table 16-3 on page 133 for details. the design of the output compare pin logic allows initialization of the oc1x state before the output is enabled. note that some com1x1:0 bit settings are reserved for certain modes of operation. see ?register description? on page 132 . the com1x1:0 bits have no effect on the input capture unit. 16.8.1 compare output mode and waveform generation the waveform generator uses the com1x1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the com1x1:0 = 0 tells the waveform generator that no action on the oc1x register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 16-1 on page 132 . for fast pwm mode refer to table 16-2 on page 132 , and for phase correct and phase and frequency correct pwm refer to table 16-3 on page 133 . a change of the com1x1:0 bits state will have effect at the first compare match after the bi ts are writt en. for non- pwm modes, the action can be forced to have immediate effect by using the foc1x strobe bits. 16.9 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm13:0) and compare output mode (com1x1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com1x1:0 bits control whether the pwm output generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the com1x1:0 bits control whether the output should be set, cleared or toggle at a compare match (see ?compare match output unit? on page 122. ) for detailed timing in formation refer to ?timer/counter timing diagrams? on page 130 . 16.9.1 normal mode the simplest mode of operation is the normal mode (wgm13:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. t he counter simply overruns when it passes its maximum 16-bit value (max = 0xffff) and then restarts from the bottom (0x0000). in normal operation the timer/coun- ter overflow flag (tov1) will be set in the same timer clock cycl e as the tcnt1 becomes zero. the tov1 flag in this case behaves like a 17th bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov1 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the input capture unit is easy to use in normal mode. however, observe that the maximum interval between the external events must not exceed the resolution of the counte r. if the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. the output compare units can be used to generate interrupts at some given time. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 16.9.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm13:0 = 4 or 12), the ocr1a or icr1 register are used to manipu- late the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt1) matches either the ocr1a (wgm13:0 = 4) or the icr1 (wgm13:0 = 12). the ocr1a or icr1 define the top value for the 124 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 16-6 . the counter value (tcnt1 ) increases until a com- pare match occurs with either ocr1a or icr1, and then counter (tcnt1) is cleared. figure 16-6. ctc mode, timing diagram an interrupt can be generated at each time the counter value reaches the top value by either using the ocf1a or icf1 flag according to the register used to define the to p value. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. howeve r, changing the top to a value close to bottom when the counter is running with none or a low prescaler va lue must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr1a or icr1 is lower than the current value of tcnt1, the counter will miss the compare match. the co unter will then have to co unt to its maximum value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. in many cases this feature is not desirable. an alternative will then be to use the fast pwm mode using ocr1a for defining top (wgm13:0 = 15) since the ocr1a then will be double buffered. for generating a waveform output in ctc mode, the oc1a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com1a1:0 = 1). the oc1a value will not be visible on the port pin unless the data direction for th e pin is set to output (ddr_oc1a = 1). the waveform generated will have a ma ximum frequency of f oc 1 a = f clk_i/o /2 when ocr1a is set to zero (0x0000). the waveform frequency is defined by the following equation: the n variable represents the prescaler factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tov1 flag is set in the same ti mer clock cycle that the counter counts from max to 0x0000. 16.9.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm13:0 = 5, 6, 7, 14, or 15) provides a high frequency pwm waveform generation option. the fast pwm differs from the other pwm options by its single-slope operation. the counter counts from bottom to top then restarts from bottom. in non-inverting compare output mode, the output compare (oc1x) is cleared on the compare match between tcnt1 and ocr1x, and set at bottom. in inverting compare output mode output is set on co mpare match and cleared at bottom. due to the single- slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase correct and phase and frequency correct pwm modes that use dual-slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac applications. high frequenc y allows physically small sized external components (coils, capacito rs), hence reduces total system cost. tcntn ocna (toggle) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 4 period 2 3 (comna1:0 = 1) f ocna f clk_i/o 2 n 1 ocrna + ?? ?? -------------------------------------------------- - = 125 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 the pwm resolution for fast pwm can be fixed to 8-, 9-, or 10-bit, or defined by either icr1 or ocr1a. the mini- mum resolution allowed is 2-bit (icr1 or ocr1a set to 0x0003), and the maximum resolution is 16-bit (icr1 or ocr1a set to max). the pwm resolution in bits can be calculated by using the following equation: in fast pwm mode the counter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgm13:0 = 5, 6, or 7), the value in icr1 (wgm13:0 = 14), or the value in ocr1a (wgm13:0 = 15). the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 16-7 . the figure shows fast pwm mode w hen ocr1a or icr1 is used to define top. the tcnt1 value is in the timing diagram shown as a histogram for illu strating the single -slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt1 slopes represent compare matches between ocr1x and tcnt1. the oc1x interrup t flag will be set when a com- pare match occurs. figure 16-7. fast pwm mode, timing diagram the timer/counter overflow flag (tov1) is set each time the counter reaches top. in addition the oc1a or icf1 flag is set at the same timer clock cyc le as tov1 is set when either ocr1a or icr1 is used for defining the top value. if one of the interrupts are enabled, the interrupt handler routine can be used for updating the top and com- pare values. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare regi sters. if the top value is lo wer than any of the compare registers, a compare match will never occur between the tcnt1 and the ocr1x. note that when using fixed top values the unused bits are masked to zero when any of the ocr1x registers are written. the procedure for updating icr1 differs from updating ocr1a when used for defining the top value. the icr1 register is not double buffered. this means that if icr1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new icr1 value written is lower than the current value of tcnt1. the result will then be that the counter will mi ss the compare match at the top value. the counter will then have to count to the max value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. the ocr1a register however, is double buffered. this feature allows the ocr1a i/o location to be written anytime. when the ocr1a i/o location is written the value written will be put into the ocr1a buffer register. the ocr1a compare register will then be updated with the value in the buffer register at the next timer clock cycle the tcnt1 matches top. the update is done at the same timer clock cycle as the tcnt1 is cleared and the tov1 flag is set. r fpwm top 1 + ?? log 2 ?? log ---------------------------------- - = tcntn ocrnx/top update and tovn interrupt flag set and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 7 period 2 3 4 5 6 8 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 126 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 using the icr1 register for defining top works well w hen using fixed top values. by using icr1, the ocr1a register is free to be used for generating a pwm output on oc1a. however, if the base pwm frequency is actively changed (by changing the top value), using the ocr1a as top is clearly a better choice due to its double buffer feature. in fast pwm mode, the compare units allow generation of pwm waveforms on the oc1x pins. setting the com1x1:0 bits to two will produce a in verted pwm and an non-inverted pwm output can be gen erated by setting the com1x1:0 to three (see table 16-3 on page 133 ). the actual oc1x value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_oc1x). the pwm waveform is generated by setting (or clearing) the oc1x register at the compare match between ocr1x and tcnt1, and clearing (or setting) the oc1x register at the timer clock cycle the co unter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr1x register represents special cases when generating a pwm waveform output in the fast pwm mode. if the ocr1x is set equal to bottom (0x0000) the output will be a narrow spike for each top+1 timer clock cycle. setting the ocr1x equal to top will result in a constant high or low output (depending on the polarity of the output set by the com1x1:0 bits.) a frequency (with 50% duty cycle) wavefo rm output in fast pwm mode can be achieved by setting oc1a to toggle its logical level on each compare match (com1a1:0 = 1). th is applies only if ocr1a is used to define the top value (wgm13:0 = 15). the waveform genera ted will have a maximum frequency of f oc 1 a = f clk_i/o /2 when ocr1a is set to zero (0x0000). this feature is similar to the oc1a toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast pwm mode. 16.9.4 phase correct pwm mode the phase correct pulse width modulation or phase correct pwm mode (wgm13:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is, like the phase and frequency correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bot- tom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (oc1x) is cleared on the compare match between tcnt1 and ocr1x while upcounting, and set on the compare match while downcounting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode can be fixed to 8-, 9-, or 10-bit, or defined by either icr1 or ocr1a. the minimum resolution allowed is 2-bit (icr1 or ocr1a set to 0x0003), and the maximum resolution is 16-bit (icr1 or ocr1a set to max). the pwm resolution in bits can be calculated by using the following equation: in phase correct pwm mode the counter is incremented until the counter value matches either one of the fixed val- ues 0x00ff, 0x01ff, or 0x03ff (wgm13:0 = 1, 2, or 3) , the value in icr1 (wgm13:0 = 10), or the value in ocr1a (wgm13:0 = 11). the counter has then reached the top and changes the count direction. the tcnt1 value will be equal to top for one time r clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 16-8 on page 127 . the figure shows phase correct pwm mode when ocr1a or icr1 is used to define top. the tcnt1 value is in the timing diagram shown as a histogram for illu strating the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt1 slopes f ocnxpwm f clk_i/o n 1 top + ?? ? ---------------------------------- - = r pcpwm top 1 + ?? log 2 ?? log ---------------------------------- - = 127 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 represent compare matches between ocr1x and tcnt1. the oc1x interrupt flag will be set when a compare match occurs. figure 16-8. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov1) is set each time the counter reaches bottom. when either ocr1a or icr1 is used for defining the top value, the oc1a or icf1 flag is set accordingly at the same timer clock cycle as the ocr1x registers are updated with the double buffer value (at top). the interrupt flags can be used to gener- ate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare regi sters. if the top value is lo wer than any of the compare registers, a compare match will never occur between the tcnt1 and the ocr1x. note that when using fixed top values, the unused bits are masked to zero when any of the ocr1x registers are written. as the third period shown in figure 16-8 on page 127 illustrates, changing the top actively while the timer/c ounter is running in the phase correc t mode can result in an unsymmetrical output. the reason for this can be f ound in the time of update of the ocr1x register. since the ocr1x update occurs at top, the pwm period starts and ends at top. this implies that the length of the fall- ing slope is determined by the previous top value, while the length of the rising slope is determined by the new top value. when these two va lues differ the two slopes of the period will differ in length. the difference in length gives the unsymmetrical result on the output. it is recommended to use the phase and frequency correct mode instead of the phase correct mode when chang- ing the top value while the timer/counter is running. when using a static top value there are practically no differences between the two modes of operation. in phase correct pwm mode, the compare units allow generation of pwm waveforms on the oc1x pins. setting the com1x1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by set- ting the com1x1:0 to three (see table 16-3 on page 133 ). the actual oc1x value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_oc1x). the pwm waveform is generated by setting (or clearing) the oc1x register at the compare matc h between ocr1x and tcnt1 when the counter increments, and clearing (or setting) the oc1x register at compare match between ocr1x and tcnt1 when the counter dec- ocrnx/top update and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tovn interrupt flag set (interrupt on bottom) tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 128 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 rements. the pwm frequency for the output when using phase correct pwm can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr1x register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr1x is set equal to bottom the output will be co ntinuously low and if set equal to top the output will be continuously high for non-inverted pwm mode. for inverted pwm the output will have the opposite logic values. if ocr1a is used to define the top value (wgm13:0 = 11) and com1a1:0 = 1, the oc1a output will toggle with a 50% duty cycle. 16.9.5 phase and frequency correct pwm mode the phase and frequency correct pulse width modulation, or phase and frequency correct pwm mode (wgm13:0 = 8 or 9) provides a high resolution phase and frequency correct pwm waveform generation option. the phase and frequency correct pwm mode is, like the phase correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting com- pare output mode, the output compare (oc1x) is cleared on the compare match between tcnt1 and ocr1x while upcounting, and set on the compare match while downcounting. in inverting compare output mode, the operation is inverted. the dual-slope operation gives a lower maximum operation frequency compared to the sin- gle-slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the main difference between the phase correct, and the phase and frequency correct pwm mode is the time the ocr1x register is updated by the ocr1x buffer register, (see figure 16-8 on page 127 and figure 16-9 on page 129 ). the pwm resolution for the phase and frequency correct pwm mode can be defined by either icr1 or ocr1a. the minimum resolution allowed is 2-bit (icr1 or ocr1a set to 0x0003), and the maximum resolution is 16-bit (icr1 or ocr1a set to max). the pwm resolution in bits can be calculated using the following equation: in phase and frequency correct pwm mode the counter is incremented until the counter value matches either the value in icr1 (wgm13:0 = 8), or the value in ocr1a (wgm13:0 = 9). the counter has then reached the top and changes the count direction. the tcnt 1 value will be equal to top for one timer clock cycle. the timing diagram for the phase correct and frequency correct pwm mode is shown on figure 16-9 on page 129 . the figure shows phase and frequency correct pwm mode when ocr1a or icr1 is used to define top. the tcnt1 value is in the timing diagram shown as a histogram for illustrating t he dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt1 slopes represent compare matches between ocr1x and tcnt1. the oc 1x interrupt flag will be set when a compare match occurs. f ocnxpcpwm f clk_i/o 2 ntop ?? --------------------------- - = r pfcpwm top 1 + ?? log 2 ?? log ---------------------------------- - = 129 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 16-9. phase and frequency correct pwm mode, timing diagram the timer/counter overflow flag (tov1) is set at the same timer clock cycle as the ocr1x registers are updated with the double buffer value (at bottom). when either ocr1a or icr1 is used for defining the top value, the oc1a or icf1 flag set when tcnt1 has reached top. the interrupt flags can then be used to generate an inter- rupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare regi sters. if the top value is lo wer than any of the compare registers, a compare match will never occur between the tcnt1 and the ocr1x. as figure 16-9 on page 129 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods. since the ocr1x registers are updated at bottom, the length of the rising and t he falling slopes will always be equal. this gives symmetrical output pulses and is therefore frequency correct. using the icr1 register for defining top works well w hen using fixed top values. by using icr1, the ocr1a register is free to be used for generating a pwm output on oc1a. however, if the base pwm frequency is actively changed by changing the top value, using the ocr1a as top is clearly a better choice due to its double buffer feature. in phase and frequency correct pwm mode, the compare units allow generation of pwm waveforms on the oc1x pins. setting the com1x1:0 bits to two will produce a non-inve rted pwm and an inverted pwm output can be gen- erated by setting the com1x1:0 to three (see table 16-3 on page 133 ). the actual oc1x va lue will only be visible on the port pin if the data direction for the port pin is set as output (ddr_oc1x). the pwm waveform is generated by setting (or clearing) the oc1x register at the compare match between ocr1x and tcnt1 when the counter increments, and clearing (or setting) the oc1x register at compare match between ocr1x and tcnt1 when the counter decrements. the pwm frequency for the output when using phase and frequency correct pwm can be cal- culated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr1x register represents special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr1x is set equal to bottom the output will be co ntinuously low and if set equal to top the output will be set to high for non-inverted pw m mode. for inverted pwm th e output will have the ocrnx/top updateand tovn interrupt flag set (interrupt on bottom) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) f ocnxpfcpwm f clk_i/o 2 ntop ?? --------------------------- - = 130 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 opposite logic values. if ocr1a is used to define the top value (wgm13:0 = 9) and com1a1:0 = 1, the oc1a output will toggle with a 50% duty cycle. 16.10 timer/counte r timing diagrams the timer/counter is a synchronous design and the timer clock (clk t1 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set, and when the ocr1x reg- ister is updated with the ocr1x buffer value (only for modes utilizing double buffering). figure 16-10 shows a timing diagram for the setting of ocf1x. figure 16-10. timer/counter timing diagram, setting of ocf1x, no prescaling figure 16-11 shows the same timing data, but with the prescaler enabled. figure 16-11. timer/counter timing diagram, setting of ocf1x, with prescaler (f clk_i/o /8) figure 16-12 on page 131 shows the count sequence close to top in various modes. when using phase and fre- quency correct pwm mode the ocr1x re gister is updated at bottom. the ti ming diagrams will be the same, but top should be replaced by bottom, top-1 by bottom+1 and so on. the same renaming applies for modes that set the tov1 flag at bottom. clk tn (clk i/o /1) ocfnx clk i/o ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) 131 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 16-12. timer/counter timing diagram, no prescaling. figure 16-13 shows the same timing data, but with the prescaler enabled. figure 16-13. timer/counter timing dia gram, with prescaler (f clk_i/o /8) tovn (fpwm) and icfn (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk tn (clk i/o /1) clk i/o tovn (fpwm) and icf n (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) 132 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 16.11 register description 16.11.1 tccr1a ? timer/counter1 control register a ? bit 7:6 ? com1a1:0: compare output mode for channel a ? bit 5:4 ? com1b1:0: compare output mode for channel b the com1a1:0 and com1b1:0 control the output compare pins (oc1a and oc1b respectively) behavior. if one or both of the com1a1:0 bits are written to one, the oc1a output overrides the normal port functionality of the i/o pin it is connected to. if one or both of the com1b1:0 bit are written to one, the oc1b output overrides the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corre- sponding to the oc1a or oc1b pin must be set in order to enable the output driver. when the oc1a or oc1b is connected to the pin, the function of the com1x1:0 bits is dependent of the wgm13:0 bits setting. table 16-1 shows the com1x1:0 bit functionality when the wgm13:0 bits are set to a normal or a ctc mode (non-pwm). table 16-2 shows the com1x1:0 bit functionality when the wgm13:0 bits are set to the fast pwm mode. note: 1. a special case occurs when ocr1a/ocr1b equals top and com1a1/com1b1 is set. in this case the compare match is ignored, but the set or clear is done at bottom. see ?fast pwm mode? on page 124 for more details. bit 76543210 (0x80) com1a1 com1a0 com1b1 com1b0 ? ? wgm11 wgm10 tccr1a read/write r/w r/w r/w r/w r r r/w r/w initial value00000000 table 16-1. compare output mode, non-pwm com1a1/com1b1 com1a0/com1b0 description 0 0 normal port operation, oc1a/oc1b disconnected. 0 1 toggle oc1a/oc1b on compare match. 10 clear oc1a/oc1b on compare match (set output to low level). 11 set oc1a/oc1b on compare match (set output to high level). table 16-2. compare output mode, fast pwm (1) com1a1/com1b1 com1a0/com1b0 description 0 0 normal port operation, oc1a/oc1b disconnected. 01 wgm13:0 = 14 or 15: toggle oc1a on compare match, oc1b disconnected (normal port operation). for all other wgm1 settings, normal port operation, oc1a/oc1b disconnected. 10 clear oc1a/oc1b on compare match, set oc1a/oc1b at bottom (non-inverting mode) 11 set oc1a/oc1b on compare match, clear oc1a/oc1b at bottom (inverting mode) 133 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 table 16-3 shows the com1x1:0 bit functionality when the wgm13:0 bits are set to the phase correct or the phase and frequency correct, pwm mode. note: 1. a special case occurs when ocr1a/ocr1b equals top and com1a1/com1b1 is set. see ?phase correct pwm mode? on page 126 for more details. ? bit 1:0 ? wgm11:0: waveform generation mode combined with the wgm13:2 bits found in the tccr1b regi ster, these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of waveform generation to be used, see table 16-4 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and three types of pulse width modulation (pwm) modes. (see ?modes of opera- tion? on page 123 ). table 16-3. compare output mode, phase correct and phase and frequency correct pwm (1) com1a1/com1b1 com1a0/com1b0 description 0 0 normal port operation, oc1a/oc1b disconnected. 01 wgm13:0 = 9 or 11: toggle oc1a on compare match, oc1b disconnected (normal port operation). for all other wgm1 settings, normal port operation, oc1a/oc1b disconnected. 10 clear oc1a/oc1b on compare match when up- counting. set oc1a/oc1b on compare match when downcounting. 11 set oc1a/oc1b on compare match when up- counting. clear oc1a/oc1b on compare match when downcounting. table 16-4. waveform generation mode bit description (1) mode wgm13 wgm12 (ctc1) wgm11 (pwm11) wgm10 (pwm10) timer/counter mode of operation top update of ocr1 x at tov1 flag set on 0 0 0 0 0 normal 0xffff immediate max 1 0 0 0 1 pwm, phase correct, 8-bit 0x00ff top bottom 2 0 0 1 0 pwm, phase correct, 9-bit 0x01ff top bottom 3 0 0 1 1 pwm, phase correct, 10-bit 0x03ff top bottom 4 0 1 0 0 ctc ocr1a immediate max 5 0 1 0 1 fast pwm, 8-bit 0x00ff bottom top 6 0 1 1 0 fast pwm, 9-bit 0x01ff bottom top 7 0 1 1 1 fast pwm, 10-bit 0x03ff bottom top 81000 pwm, phase and frequency correct icr1 bottom bottom 91001 pwm, phase and frequency correct ocr1a bottom bottom 10 1 0 1 0 pwm, phase correct icr1 top bottom 11 1 0 1 1 pwm, phase correct ocr1a top bottom 12 1 1 0 0 ctc icr1 immediate max 134 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. the ctc1 and pwm11:0 bit defi nition names are obsolete. use the wgm 12:0 definitions. however, the functionality and location of these bits are compatible with previous versions of the timer. 16.11.2 tccr1b ? timer/counter1 control register b ? bit 7 ? icnc1: input capture noise canceler setting this bit (to one) activates the input capture noise canceler. when the noise canceler is activated, the input from the input capture pin (icp1) is filtered. the filter function requires four successive equal valued samples of the icp1 pin for ch anging its output. the in put capture is th erefore delayed by four os cillator cycl es when the noise canceler is enabled. ? bit 6 ? ices1: input capture edge select this bit selects which edge on the input capture pin (icp1) that is used to trigger a capture event. when the ices1 bit is written to zero, a fallin g (negative) edge is used as trigger, and wh en the ices1 bit is written to one, a rising (positive) edge will trigger the capture. when a capture is triggered according to the ices1 setting , the counter value is copied into the input capture reg- ister (icr1). the event will also set the input ca pture flag (icf1), and this can be used to cause an input capture interrupt, if this interrupt is enabled. when the icr1 is used as top value (see description of the wgm13:0 bits located in the tccr1a and the tccr1b register), the icp1 is disconnected and co nsequently the input capture function is disabled. ? bit 5 ? reserved this bit is reserved for future use. for ensuring compatibili ty with future devices, this bit must be written to zero when tccr1b is written. ? bit 4:3 ? wgm13:2: waveform generation mode see tccr1a register description. ? bit 2:0 ? cs12:0: clock select the three clock select bits select the clock so urce to be used by the timer/counter, see figure 16-10 on page 130 and figure 16-11 on page 130 . 13 1 1 0 1 (reserved) ? ? ? 14 1 1 1 0 fast pwm icr1 bottom top 15 1 1 1 1 fast pwm ocr1a bottom top table 16-4. waveform generation mode bit description (1) (continued) mode wgm13 wgm12 (ctc1) wgm11 (pwm11) wgm10 (pwm10) timer/counter mode of operation top update of ocr1 x at tov1 flag set on bit 7 6 5 4 3 2 1 0 (0x81) icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 tccr1b read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 135 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 if external pin modes are used for the timer/counter1, transitions on the t1 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 16.11.3 tccr1c ? timer/counter1 control register c ? bit 7 ? foc1a: force output compare for channel a ? bit 6 ? foc1b: force output compare for channel b the foc1a/foc1b bits are only active when the wgm13:0 bits specifies a non-pwm mode. when writing a logi- cal one to the foc1a/foc1b bit, an immediate compare match is forced on the waveform generation unit. the oc1a/oc1b output is changed according to its com1x1:0 bits setting. note that the foc1a/foc1b bits are implemented as strobes. therefore it is the value present in the com1x1:0 bits that determine the effect of the forced compare. a foc1a/foc1b strobe will not generate any interrupt nor will it clear the ti mer in clear timer on compare match (ctc) mode using ocr1a as top. the foc1a/foc1b bits are always read as zero. 16.11.4 tcnt1h and tcnt1l ? timer/counter1 the two timer/counter i/o locations (tcnt1h and tcnt1l, combined tcnt1) give direct access, both for read and for write operations, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 114 . modifying the counter (tcnt1) while the counter is running introduces a risk of missing a compare match between tcnt1 and one of the ocr1x registers. table 16-5. clock select bit description cs12 cs11 cs10 description 0 0 0 no clock source (timer/counter stopped). 001clk i/o /1 (no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t1 pin. clock on falling edge. 1 1 1 external clock source on t1 pin. clock on rising edge. bit 7 6 5 4 3 2 1 0 (0x82) foc1a foc1b ? ? ? ? ? ? tccr1c read/write r/w r/w r r r r r r initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x85) tcnt1[15:8] tcnt1h (0x84) tcnt1[7:0] tcnt1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 136 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 writing to the tcnt1 register blocks (removes) the comp are match on the following timer clock for all compare units. 16.11.5 ocr1ah and ocr1al ? ou tput compare register 1 a 16.11.6 ocr1bh and ocr1bl ? ou tput compare register 1 b the output compare registers contain a 16-bit value t hat is continuously compared with the counter value (tcnt1). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc1x pin. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultane- ously when the cpu writes to these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 114 . 16.11.7 icr1h and icr1l ? input capture register 1 the input capture is updated with the counter (tcnt1) value each time an event occurs on the icp1 pin (or optionally on the analog comparator output for timer/counter1). the input capture can be used for defining the counter top value. the input capture register is 16-bit in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 114 . 16.11.8 timsk1 ? timer/counter 1 interrupt mask register ? bit 7, 6 ? reserved these bits are unused bits in the atmega48a/pa/ 88a/pa/168a/pa/328/p, and w ill always read as zero. bit 76543210 (0x89) ocr1a[15:8] ocr1ah (0x88) ocr1a[7:0] ocr1al read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x8b) ocr1b[15:8] ocr1bh (0x8a) ocr1b[7:0] ocr1bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x87) icr1[15:8] icr1h (0x86) icr1[7:0] icr1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x6f) ? ? icie1 ? ? ocie1b ocie1a toie1 timsk1 read/write r r r/w r r r/w r/w r/w initial value00000000 137 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bit 5 ? icie1: timer/counter1, input capture interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 input capture interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 57 ) is executed when the icf1 flag, located in tifr1, is set. ? bit 4, 3 ? reserved these bits are unused bits in the atmega48a/pa/ 88a/pa/168a/pa/328/p, and w ill always read as zero. ? bit 2 ? ocie1b: timer/counter1, output compare b match interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 output compare b match interrupt is enabled. the corresponding interrupt vector ( see ?inter- rupts? on page 57 ) is executed when the ocf1b flag, located in tifr1, is set. ? bit 1 ? ocie1a: timer/counter1, output compare a match interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 output compare a match interrupt is enabled. the corresponding interrupt vector ( see ?inter- rupts? on page 57 ) is executed when the ocf1a flag, located in tifr1, is set. ? bit 0 ? toie1: timer/counte r1, overflow interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 overflow interrupt is enabled . the corresponding interrupt vector (see ?interrupts? on page 57 ) is executed when the tov1 flag, located in tifr1, is set. 16.11.9 tifr1 ? timer/counter1 interrupt flag register ? bit 7, 6 ? reserved these bits are unused bits in the atmega48a/pa/ 88a/pa/168a/pa/328/p, and w ill always read as zero. ? bit 5 ? icf1: timer/counter1, input capture flag this flag is set when a capture event occurs on the icp1 pin. when the input capture register (icr1) is set by the wgm13:0 to be used as the top value, the icf1 flag is set when the counter reaches the top value. icf1 is automatically cleared when the input capture interrupt vector is executed. alternatively, icf1 can be cleared by writing a logic one to its bit location. ? bit 4, 3 ? reserved these bits are unused bits in the atmega48a/pa/ 88a/pa/168a/pa/328/p, and w ill always read as zero. ? bit 2 ? ocf1b: timer/counter1, output compare b match flag this flag is set in the timer clock cycle after the count er (tcnt1) value matches the output compare register b (ocr1b). note that a forced output compare (foc 1b) strobe will not set the ocf1b flag. ocf1b is automatically cleared when the output compare match b interrupt vector is executed. alternatively, ocf1b can be cleared by writing a logic one to its bit location. bit 76543210 0x16 (0x36) ? ? icf1 ? ? ocf1b ocf1a tov1 tifr1 read/write r r r/w r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 138 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bit 1 ? ocf1a: timer/counter1, output compare a match flag this flag is set in the timer clock cycle after the count er (tcnt1) value matches the output compare register a (ocr1a). note that a forced output compare (foc 1a) strobe will not set the ocf1a flag. ocf1a is automatically cleared when the output compare match a interrupt vector is executed. alternatively, ocf1a can be cleared by writing a logic one to its bit location. ? bit 0 ? tov1: timer/c ounter1, overflow flag the setting of this flag is dependent of the wgm13:0 bits setting. in normal and ctc modes, the tov1 flag is set when the timer overflows. refer to table 16-4 on page 133 for the tov1 flag behavior when using another wgm13:0 bit setting. tov1 is automatically cleared when the timer/counter1 overflow interrupt vector is executed. alternatively, tov1 can be cleared by writing a logic one to its bit location. 139 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 17. timer/counter0 and ti mer/counter1 prescalers ?8-bit timer/counter0 with pwm? on page 94 and ?16-bit timer/counter1 with pwm? on page 112 share the same prescaler module, but the timer/counters can have different prescaler settings. the description below applies to both timer/counter1 and timer/counter0. 17.1 internal clock source the timer/counter can be clocked directly by the system cl ock (by setting the csn2:0 = 1). this provides the fast- est operation, with a maximum timer/counter clock frequency equal to system clock frequency (f clk_i/o ). alternatively, one of four taps from the prescaler can be used as a clock source. t he prescaled clock has a fre- quency of either f clk_i/o /8, f clk_i/o /64, f clk_i/o /256, or f clk_i/o /1024. 17.2 prescaler reset the prescaler is free running, i.e., operates independently of the clock select logic of the timer/counter, and it is shared by timer/counter1 and timer/c ounter0. since the prescaler is not affected by the timer/counter?s clock select, the state of the prescaler will ha ve implications for situations where a prescaled clock is used. one example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > csn2:0 > 1). the number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to n+1 system clock cycles, where n equals the prescaler divisor (8, 64, 256, or 1024). it is possible to use the prescaler reset for synchronizi ng the timer/counter to program execution. however, care must be taken if the other timer/counter that shares the same prescaler also uses prescaling. a prescaler reset will affect the prescaler period for all timer/counters it is connected to. 17.3 external clock source an external clock source applied to the t1/t0 pin can be used as timer/counter clock (clk t1 /clk t0 ). the t1/t0 pin is sampled once every system clock c ycle by the pin synchronization logic. the synchronized (sampled) signal is then passed through the edge detector. figure 17-1 shows a functional equivalent block diagram of the t1/t0 syn- chronization and edge detector logic. the registers are cloc ked at the positive edge of the internal system clock ( clk i/o ). the latch is transparent in the high period of the internal system clock. the edge detector generates one clk t1 /clk t 0 pulse for each positive (csn2:0 = 7) or negative (csn2:0 = 6) edge it detects. figure 17-1. t1/t0 pin sampling the synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the t1/t0 pin to the counter is updated. enabling and disabling of the clock input must be done when t1/t0 has been stable for at least one system clock cycle, otherwise it is a risk that a false timer/counter clock pulse is generated. each half period of the external clock applied must be longer than one system clock cycle to ensure correct sam- pling. the external clock must be guaranteed to have less than half the system clock frequency (f extclk < f clk_i/o /2) tn_sync (to clock select logic) edge detector synchronization dq dq le dq tn clk i/o 140 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 given a 50/50% duty cycle. since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (nyquist sampling theorem). however, due to variation of the system clock frequency and duty cycle caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is rec- ommended that maximum frequency of an external clock source is less than f clk_i/o /2.5. an external clock source can not be prescaled. figure 17-2. prescaler for timer/counter0 and timer/counter1 (1) note: 1. the synchronization logic on the input pins ( t1/t0) is shown in figure 17-1 . psrsync clear clk t1 clk t0 t1 t0 clk i/o synchronization synchronization 141 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 17.4 register description 17.4.1 gtccr ? general timer/counter control register ? bit 7 ? tsm: timer/counter synchronization mode writing the tsm bit to one activates the timer/counter synchronization mode. in this mode, the value that is writ- ten to the psrasy and psrsync bits is kept, hence keeping the corresponding prescaler reset signals asserted. this ensures that the corresponding timer/counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. when the tsm bit is wri tten to zero, the psrasy and psrsync bits are cleared by hardware, and the timer/counters start counting simultaneously. ? bit 0 ? psrsync: prescaler reset when this bit is one, timer/counter1 and timer/coun ter0 prescaler will be reset. this bit is normally cleared immediately by hardware, except if the tsm bit is set. note that timer/counter1 and timer/counter0 share the same prescaler and a reset of this prescaler will affect both timers. bit 765432 1 0 0x23 (0x43) tsm ? ? ? ? ? psrasy psrsync gtccr read/write r/w r r r r r r/w r/w initial value000000 0 0 142 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 18. 8-bit timer/counter2 with pwm and asynchronous operation 18.1 features ? single channel counter ? clear timer on compare match (auto reload) ? glitch-free, phase correct pu lse width modulator (pwm) ? frequency generator ? 10-bit clock prescaler ? overflow and compare match interrup t sources (tov2, ocf2a and ocf2b) ? allows clocking from external 32khz watc h crystal independent of the i/o clock 18.2 overview timer/counter2 is a general purpose, single channel, 8-bi t timer/counter module. a simplified block diagram of the 8-bit timer/counter is shown in figure 18-1 . for the actual placement of i/o pins, refer to ?pinout atmega48a/pa/88a/pa/168a/ pa/328/p? on page 2 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o r egister and bit locations are listed in the ?register description? on page 155 . the prtim2 bit in ?minimizing power consumption? on page 41 must be written to zero to enable timer/counter2 module. figure 18-1. 8-bit timer/counter block diagram 18.2.1 registers the timer/counter (tcnt2) and output compare register (ocr2a and ocr2b) are 8-bit registers. interrupt request (shorten as int.req.) signals are all visible in the timer interrupt flag register (tifr2). all interrupts are clock select timer/counter data bus ocrna ocrnb = = tcntn waveform generation waveform generation ocna ocnb = fixed top value control logic = 0 top bottom count clear direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) tccrna tccrnb tn edge detector ( from prescaler ) clk tn 143 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 individually masked with the timer interrupt mask register (timsk2). tifr2 and timsk2 are not shown in the figure. the timer/counter can be clocked internally, via the presca ler, or asynchronously clocked from the tosc1/2 pins, as detailed later in this section. the asynchronous operation is controlled by the asynchronous status register (assr). the clock select logic block controls which clock source he timer/ counter uses to increment (or decre- ment) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t2 ). the double buffered output compare register (ocr2a and ocr2b) are compared with the timer/counter value at all times. the result of the compare can be used by the waveform generator to generate a pwm or variable fre- quency output on the output compare pins (oc2a and oc2b). see ?output compare unit? on page 144 for details. the compare match ev ent will also set the compare flag (ocf2a or ocf2b) which can be used to gener- ate an output compare interrupt request. 18.2.2 definitions many register and bit references in this document are written in general form. a lower case ?n? replaces the timer/counter number, in this case 2. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt2 for accessing timer/counter2 counter value and so on. the definitions in table 18-1 are also used extensively throughout the section. table 18-1. definitions 18.3 timer/counter clock sources the timer/counter can be clocked by an internal synchronous or an external asynchronous clock source. the clock source clk t2 is by default equal to the mcu clock, clk i/o . when the as2 bit in the assr register is written to logic one, the clock source is taken from the timer/ counter oscillator connected to tosc1 and tosc2. for details on asynchronous operation, see ?assr ? asynchronous stat us register? on page 160 . for details on clock sources and prescaler, see ?timer/counter prescaler? on page 154 . 18.4 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 18-2 on page 143 shows a block diagram of the counter and its surrounding environment. figure 18-2. counter unit block diagram bottom the counter reaches the bottom when it becomes zero (0x00). max the counter reaches its maximum when it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr2a register. the assignment is depen- dent on the mode of operation. data b u s tcntn control logic count tovn (int.req.) top bottom direction clear tosc1 t/c oscillator tosc2 prescaler clk i/o clk tn 144 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 signal description (internal signals): count increment or decrement tcnt2 by 1. direction selects between increment and decrement. clear clear tcnt2 (set a ll bits to zero). clk tn timer/counter clock, referred to as clk t2 in the following. top signalizes that tcnt2 has reached maximum value. bottom signalizes that tcnt2 has reached minimum value (zero). depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t2 ). clk t2 can be generated from an external or internal clock source, selected by the clock select bits (cs22:0). when no clock source is selected (cs22:0 = 0) the timer is stopped. however, the tcnt2 value can be accessed by the cpu, regardless of whether clk t2 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the wgm21 and wgm20 bits located in the timer/counter control register (tccr2a) and the wgm22 located in t he timer/counter control register b (tccr2b). there are close connections between how t he counter behaves (counts) and how waveforms are generated on the out- put compare outputs oc2a and oc2b. for more deta ils about advanced counting sequences and waveform generation, see ?modes of operation? on page 147 . the timer/counter overflow flag (tov2) is set according to the mode of operation selected by the wgm22:0 bits. tov2 can be used for generating a cpu interrupt. 18.5 output compare unit the 8-bit comparator continuously compares tcnt2 with the output compare register (ocr2a and ocr2b). whenever tcnt2 equals ocr2a or ocr2b, the comparator signals a match. a match will set the output com- pare flag (ocf2a or ocf2b) at the next timer clock c ycle. if the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. the output compare flag is automatically cleared when the interrupt is executed. alternatively, the output co mpare flag can be cleared by soft ware by writing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to oper- ating mode set by the wgm22:0 bits and compare output mode (com2x1:0) bits. the max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of oper- ation ( ?modes of operation? on page 147 ). figure 18-3 shows a block diagram of the output compare unit. 145 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 18-3. output compare unit, block diagram the ocr2x register is double buffered when using any of the pulse width modulation (pwm) modes. for the nor- mal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocr2x compare register to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr2x register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocr2x buffer regi ster, and if double buffering is di sabled the cpu will access the ocr2x directly. 18.5.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (foc2x) bit. forcing compare match will not set the ocf2x flag or reload/clear the timer, but the oc2x pin will be updated as if a real compare match had occurred (the com2x1:0 bits settings define whether the oc2x pin is set, cleared or toggled). 18.5.2 compare match bloc king by tcnt2 write all cpu write operations to the tcnt2 register will blo ck any compare match that occurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocr2x to be initialized to the same value as tcnt2 without triggering an interrupt when the timer/counter clock is enabled. 18.5.3 using the output compare unit since writing tcnt2 in any mode of operatio n will block all compare matches fo r one timer clock cycle, there are risks involved when changing tcnt2 when using the outp ut compare channel, indepe ndently of whether the timer/counter is runnin g or not. if the value written to tcnt2 equals the ocr2x va lue, the compare match will be missed, resulting in incorrect waveform generation. sim ilarly, do not write the tcnt2 value equal to bottom when the counter is downcounting. the setup of the oc2x should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc2x value is to use the force output compare (foc2x) strobe bit in normal mode. the oc2x register keeps its value even wh en changing between waveform generation modes. ocfn x (int.req.) = (8-bit comparator ) ocrnx ocnx data b u s tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 146 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 be aware that the com2x1:0 bits are not double buffered together with the compare value. changing the com2x1:0 bits will take effect immediately. 18.6 compare match output unit the compare output mode (com2x1:0) bits have two f unctions. the waveform generator uses the com2x1:0 bits for defining the output compare (oc2x) state at the next compare match. also, the com2x1:0 bits control the oc2x pin output source. figure 18-4 shows a simplified schematic of the logic affected by the com2x1:0 bit set- ting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com2x1:0 bits are shown. when referring to the oc2x state, the reference is for the internal oc2x register, not the oc2x pin. figure 18-4. compare match output unit, schematic the general i/o port function is overridden by the outp ut compare (oc2x) from the waveform generator if either of the com2x1:0 bits are set. however, the oc2x pin direct ion (input or output) is still controlle d by the data direc- tion register (ddr) for the port pin. the data direction register bit for the oc2x pin (ddr_oc2x) must be set as output before the oc2x value is visible on the pin. th e port override function is independent of the waveform gen- eration mode. the design of the output compare pin logic allows initialization of the oc2x state before the output is enabled. note that some com2x1:0 bit settings are reserved for certain modes of operation. see ?register description? on page 155 18.6.1 compare output mode and waveform generation the waveform generator uses the com2x1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the com2x1:0 = 0 tells the waveform generator that no action on the oc2x register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 18-5 on page 156 . for fast pwm mode, refer to table 18-6 on page 156 , and for phase correct pwm refer to table 18-7 on page 157 . a change of the com2x1:0 bits state will have effect at the first compare match after the bi ts are writt en. for non- pwm modes, the action can be forced to have immediate effect by using the foc2x strobe bits. port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data b u s focnx clk i/o 147 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 18.7 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm22:0) and compare output mode (com2x1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com2x1:0 bits control whether the pwm output generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the com2x1:0 bits control whether the output should be set, cleared, or toggled at a compare match (see ?compare match output unit? on page 146 ). for detailed timing in formation refer to ?timer/counter timing diagrams? on page 151 . 18.7.1 normal mode the simplest mode of operation is the normal mode (wgm22 :0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 8- bit value (top = 0xff) and then restarts from the bott om (0x00). in normal operation the timer/counter overflow flag (tov2) will be set in the same ti mer clock cycle as the tcnt2 become s zero. the tov2 flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov2 flag, the timer reso lution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 18.7.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm22:0 = 2), the ocr2a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt2) matches the ocr2a. the ocr2a defines the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifie s the operation of counting external events. the timing diagram for the ctc mode is shown in figure 18-5 . the counter value (tcnt2 ) increases until a com- pare match occurs between tcnt2 and ocr2a, and then counter (tcnt2) is cleared. figure 18-5. ctc mode, timing diagram an interrupt can be generated each time the counter value reaches the top value by using the ocf2a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a value close to bottom when the counter is runni ng with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr2a is lower than the current value of tcnt2, the counter will miss the compare match. the count er will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, the oc2a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com2a1:0 = 1). the oc2a value will tcntn ocnx (toggle) ocnx interrupt flag set 1 4 period 2 3 (comnx1:0 = 1) 148 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 not be visible on the port pin unless the data direction for the pin is set to output. the waveform generated will have a maximum frequency of f oc2a = f clk_i/o /2 when ocr2a is set to zero (0x00). the waveform frequency is defined by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). as for the normal mode of operation, the tov2 flag is set in the same timer clock cycle that the counter counts from max to 0x00. 18.7.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm22:0 = 3 or 7) provides a high frequency pwm wave- form generation option. the fast pwm differs from the other pwm option by its single-slope operation. the counter counts from bottom to top then restarts from bottom. top is defined as 0xff when wgm2:0 = 3, and ocr2a when mgm2:0 = 7. in non-inverting compare output mode, the output compare (oc2x) is cleared on the compare match between tcnt2 and ocr2x, and set at bottom. in inverting compare output mode, the output is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase co rrect pwm mode that uses dual-slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac applications. high frequency allows physically small sized external co mponents (coils, capacitors), and therefore reduces total system cost. in fast pwm mode, the counter is incremented until the counter value matches the top value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 18-6 . the tcnt2 value is in the timing diagram shown as a histogram for illustrating the single-slope op eration. the diagram includes non-inverted and inverted pwm outputs. the sma ll horizontal line marks on the tcnt2 slopes represent compare matches between ocr2x and tcnt2. figure 18-6. fast pwm mode, timing diagram the timer/counter overflow flag (tov2) is set each time the counter reaches top. if the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. in fast pwm mode, the compare unit allows generation of pwm waveforms on the oc2x pin. setting the com2x1:0 bits to two will produce a non-inverted pwm and an inverted pwm ou tput can be gener ated by setting f ocnx f clk_i/o 2 n 1 ocrnx + ?? ?? ------------------------------------------------- - = tcntn ocrnx update and tovn interrupt flag set 1 period 2 3 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag set 4 5 6 7 149 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 the com2x1:0 to three. top is defined as 0xff when wgm2:0 = 3, and ocr2a when mgm2:0 = 7. (see table 18-3 on page 155 ). the actual oc2x valu e will only be visible on the port pin if th e data direction for the port pin is set as output. the pwm waveform is generated by setting (o r clearing) the oc2x register at the compare match between ocr2x and tcnt2, and clearing (or setting) the oc2x register at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a pwm waveform output in the fast pwm mode. if the ocr2a is set equal to bottom, the ou tput will be a narrow spike for each max+1 timer clock cycle. setting the ocr2a equal to max will resu lt in a constantly high or low output (depending on the polarity of the output set by the com2a1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast pwm mode can be achieved by setting oc2x to toggle its logical level on each compare match (com2x1:0 = 1). the waveform generated will have a maximum frequency of f oc2 = f clk_i/o /2 when ocr2a is set to zero. this feature is similar to the oc2a toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast pwm mode. 18.7.4 phase correct pwm mode the phase correct pwm mode (wgm22:0 = 1 or 5) provides a high resolution phase correct pwm waveform gen- eration option. the phase correct pwm mode is based on a dual-slope operation. the counter counts repeatedly from bottom to top and then from top to bottom. top is defined as 0xff when wgm2:0 = 3, and ocr2a when mgm2:0 = 7. in non-inverting compare output mode, the output compare (oc2x) is cleared on the com- pare match between tcnt2 and ocr2x while upcounting, and set on the compare match while downcounting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. in phase correct pwm mode the counter is incremented unt il the counter value matches top. when the counter reaches top, it change s the count direction. the tcnt2 value will be eq ual to top for one ti mer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 18-7 . the tcnt2 value is in the timing dia- gram shown as a histogram for illu strating the dua l-slope operatio n. the diagram incl udes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt2 slopes represent compare matches between ocr2x and tcnt2. f ocnxpwm f clk_i/o n 256 ? ------------------ = 150 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 18-7. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov2) is set each ti me the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct pwm mode, the compare unit allows generation of pwm waveforms on the oc2x pin. setting the com2x1:0 bits to two will produce a non-inverted pwm. an inverted pwm ou tput can be generat ed by setting the com2x1:0 to three. top is defined as 0xff when wgm2:0 = 3, and ocr2a when mgm2:0 = 7 (see table 18-4 on page 155 ). the actual oc2x value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm waveform is generated by clearing (or setting) the oc2x register at the compare match between ocr2x and tcnt2 when the counter increments, and setting (or clearing) the oc2x register at compare match between ocr2x and tcnt2 when the counter decrements. the pwm frequency for the output when using phase correct pwm can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the o cr2a is set equal to bottom, the outp ut will be continuously low and if set equal to max the output will be continuously high for non-inverted pwm mode. for inverted pwm the output will have the opposite logic values. at the very start of period 2 in figure 18-7 ocnx has a transition from high to low even though there is no compare match. the point of this transition is to guarantee symmetry around bottom. there are two cases that give a transition without compare match. ? ocr2a changes its valu e from max, like in figure 18-7 . when the ocr2a value is max the ocn pin value is the same as the result of a down-counting compare match. to ensure symmetry around bottom the ocn value at max must correspond to the result of an up-counting compare match. ? the timer starts counting from a value higher than the one in ocr2a, and for that reason misses the compare match and hence the ocn change that would have happened on the way up. tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx update f ocnxpcpwm f clk_i/o n 510 ? ------------------ = 151 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 18.8 timer/counter timing diagrams the following figures show the timer/counter in synchronous mode, and the timer clock (clk t2 ) is therefore shown as a clock enable signal. in asynchronous mode, clk i/o should be replaced by the timer/counter oscillator clock. the figures include information on when interrupt flags are set. figure 18-8 contains timing data for basic timer/counter operation. the figure shows the count s equence close to the max value in all modes other than phase correct pwm mode. figure 18-8. timer/counter timing diagram, no prescaling figure 18-9 shows the same timing data, but with the prescaler enabled. figure 18-9. timer/counter timing dia gram, with prescaler (f clk_i/o /8) figure 18-10 shows the setting of ocf2a in all modes except ctc mode. figure 18-10. timer/counter timing diagram, sett ing of ocf2a, with prescaler (f clk_i/o /8) figure 18-11 shows the setting of ocf2a and the clearing of tcnt2 in ctc mode. clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) 152 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 18-11. timer/counter timing diagram, clear timer on compare match mode, with prescaler (f clk_i/o /8) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) 153 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 18.9 asynchronous operati on of timer/counter2 when timer/counter2 operates asynchronously, some considerations must be taken. ? warning: when switching between asynchronous and synchronous clocking of timer/counter2, the timer registers tcnt2, ocr2x, and tccr2x might be corrupted. a safe procedure for switching clock source is: a. disable the timer/counter2 interrupts by clearing ocie2x and toie2. b. select clock source by setting as2 as appropriate. c. write new values to tcnt2, ocr2x, and tccr2x. d. to switch to asynchronous operation: wait for tcn2xub, ocr2xub, and tcr2xub. e. clear the timer/counter2 interrupt flags. f. enable interrupts, if needed. ? the cpu main clock frequency must be more than four times th e oscillator frequency. ? when writing to one of the registers tcnt2, ocr2x, or tccr2x, the value is transferred to a temporary register, and latched after two positive edges on tosc1. the user should not write a new value before the contents of the temporary register have been transferred to its destination. each of the five mentioned registers have their individual temporary register, which means that e.g. writing to tcnt2 does not disturb an ocr2x write in progress. to detect that a transfer to the destination register has taken place, the asynchronous status register ? assr has been implemented. ? when entering power-save or adc noise reduction mode after having written to tc nt2, ocr2x, or tccr2x, the user must wait until the written register has been updated if timer/counter2 is used to wake up the device. otherwise, the mcu will enter sl eep mode before the ch anges are effective. this is par ticularly important if any of the output compare2 interrupt is used to wake up the device, since the output compare function is disabled during writing to ocr2x or tcnt2. if the write cycle is not finished, and the mcu enters sleep mode before the corresponding ocr2xub bit returns to zero, the device will never receive a compare match interrupt, and the mcu will not wake up. ? if timer/counter2 is used to wake the device up from power-save or adc noise reduction mode, precautions must be taken if the user wants to re-enter one of these modes: if re-entering sleep mode within the tosc1 cycle, the interrupt will immediately occu r and the device wake up again. the result is multiple interrupts and wake-ups within one tosc1 cycle from the first interrupt. if the user is in doubt w hether the time before re- entering power-save or adc noise reduction mode is suff icient, the following algorithm can be used to ensure that one tosc1 cycle has elapsed: a. write a value to tccr2x, tcnt2, or ocr2x. b. wait until the corresponding update busy flag in assr returns to zero. c. enter power-save or adc noise reduction mode. ? when the asynchronous operation is selected, the 32 .768khz oscillator for timer/counter2 is always running, except in power-down and standby modes. after a power-up reset or wake-up from power-down or standby mode, the user should be aware of the fact that this oscillator might take as long as one second to stabilize. the user is advised to wait for at least one second before using timer/counter2 after power-up or wake-up from power-down or standby mode. the contents of all timer/counter2 registers must be considered lost after a wake-up from power-down or standby mode due to unstable clock signal upon start-up, no matter whether the oscillator is in use or a clock si gnal is applied to the tosc1 pin. ? description of wake up from power-save or adc noise reduction mode when the timer is clocked asynchronously: when the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. after wake-up, the mcu is halted for four cycles, it ex ecutes the interrupt routine, and resumes execution from the instruction following sleep. 154 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? reading of the tcnt2 register shortly after wake-up from power-save may give an incorrect result. since tcnt2 is clocked on the asynchronous tosc clock, reading tcnt2 must be done through a register synchronized to the internal i/o clock domain. synchronization takes place for every rising tosc1 edge. when waking up from power-save mode, and the i/o clock (clk i/o ) again becomes active, tcnt2 will read as the previous value (before entering sleep) until the next rising tosc1 edge. the phase of the tosc clock after waking up from power-save mode is essentially unp redictable, as it depends on the wake-up time. the recommended procedure for reading tcnt2 is thus as follows: a. write any value to either of the registers ocr2x or tccr2x. b. wait for the corresponding update busy flag to be cleared. c. read tcnt2. during asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes 3 processor cycles plus one timer cycle. the timer is ther efore advanced by at least one before the processor can read the timer value causing the setting of the interrupt flag. the output compare pin is changed on the timer clock and is not synchronized to the processor clock. 18.10 timer/counter prescaler figure 18-12. prescaler for timer/counter2 the clock source for timer/counter2 is named clk t2s . clk t2s is by default connected to the main system i/o clock clk i o . by setting the as2 bit in assr, timer/counter2 is asynchronously clocked from the tosc1 pin. this enables use of timer/counter2 as a real time counter (rtc). when as2 is set, pins tosc1 and tosc2 are dis- connected from port b. a crystal can then be connec ted between the tosc1 and tosc2 pins to serve as an independent clock source for timer/ counter2. the oscillator is optimiz ed for use with a 32.768khz crystal. for timer/counter2, the possible prescaled selections are: clk t2s /8, clk t2s /32, clk t2s /64, clk t2s /128, clk t2s /256, and clk t2s /1024. additionally, clk t2s as well as 0 (stop) may be selected. setting the psrasy bit in gtccr resets the prescaler. this allows the user to operate with a predictable prescaler. 10-bit t/c prescaler timer/counter2 clock source clk i/o clk t2s tosc1 as2 cs20 cs21 cs22 clk t2s /8 clk t2s /64 clk t2s /128 clk t2s /1024 clk t2s /256 clk t2s /32 0 psrasy clear clk t2 155 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 18.11 register description 18.11.1 tccr2a ? timer/counter control register a ? bits 7:6 ? com2a1:0: compare match output a mode these bits control the output compare pin (oc2a) behavior. if one or both of the com2a1:0 bits are set, the oc2a output overrides the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corresponding to the oc2a pin must be set in order to enable the output driver. when oc2a is connected to the pin, the function of the com2a1:0 bits depends on the wgm22:0 bit setting. table 18-2 shows the com2a1:0 bit functionality when the wgm22:0 bits are set to a normal or ctc mode (non- pwm). table 18-3 shows the com2a1:0 bit functionality when the wgm21:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr2a equals top and com2 a1 is set. in this case, the compare match is ignored, but the set or clear is done at bottom. see ?fast pwm mode? on page 148 for more details. table 18-4 shows the com2a1:0 bit functionality when the wgm22:0 bits are set to phase correct pwm mode. bit 7 6 5 4 3 210 (0xb0) com2a1 com2a0 com2b1 com2b0 ? ? wgm21 wgm20 tccr2a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 18-2. compare output mode, non-pwm mode com2a1 com2a0 description 0 0 normal port operation, oc0a disconnected. 0 1 toggle oc2a on compare match 1 0 clear oc2a on compare match 1 1 set oc2a on compare match table 18-3. compare output mode, fast pwm mode (1) com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 01 wgm22 = 0: normal port operation, oc0a disconnected. wgm22 = 1: toggle oc2a on compare match. 10 clear oc2a on compare match, set oc2a at bottom, (non-inverting mode). 11 set oc2a on compare match, clear oc2a at bottom, (inverting mode). table 18-4. compare output mode, phase correct pwm mode (1) com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 156 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. a special case occurs when ocr2a equals top and com2 a1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 149 for more details. ? bits 5:4 ? com2b1:0: compare match output b mode these bits control the output compare pin (oc2b) behavior. if one or both of the com2b1:0 bits are set, the oc2b output overrides the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corresponding to the oc2b pin must be set in order to enable the output driver. when oc2b is connected to the pin, the function of the com2b1:0 bits depends on the wgm22:0 bit setting. table 18-5 shows the com2b1:0 bit functionality when the wgm22:0 bits are set to a normal or ctc mode (non- pwm). table 18-6 shows the com2b1:0 bit functionality when the wgm22:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr2b equals top and com2 b1 is set. in this case, the compare match is ignored, but the set or clear is done at bottom. see ?phase correct pwm mode? on page 149 for more details. 01 wgm22 = 0: normal port o peration, oc2a disconnected. wgm22 = 1: toggle oc2a on compare match. 10 clear oc2a on compare match when up-counting. set oc2a on compare match when down-counting. 11 set oc2a on compare match when up-counting. clear oc2a on compare match when down-counting. table 18-5. compare output mode, non-pwm mode com2b1 com2b0 description 0 0 normal port operation, oc2b disconnected. 0 1 toggle oc2b on compare match 1 0 clear oc2b on compare match 1 1 set oc2b on compare match table 18-6. compare output mode, fast pwm mode (1) com2b1 com2b0 description 0 0 normal port operation, oc2b disconnected. 01reserved 10 clear oc2b on compare match, set oc2b at bottom, (non-inverting mode). 11 set oc2b on compare match, clear oc2b at bottom, (inverting mode). table 18-4. compare output mode, phase correct pwm mode (1) com2a1 com2a0 description 157 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 table 18-7 shows the com2b1:0 bit functionality when the wgm22:0 bits are set to phase correct pwm mode. note: 1. a special case occurs when ocr2b equals top and com2 b1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 149 for more details. ? bits 3:2 ? reserved these bits are reserved in the atmega48a/pa/88a/pa/168a/pa/328/p and will always read as zero. ? bits 1:0 ? wgm21:0: waveform generation mode combined with the wgm22 bit found in the tccr2b regist er, these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of waveform generation to be used, see table 18-8 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes (see ?modes of operation? on page 147 ). notes: 1. max= 0xff 2. bottom= 0x00 table 18-7. compare output mode, phase correct pwm mode (1) com2b1 com2b0 description 0 0 normal port operation, oc2b disconnected. 01reserved 10 clear oc2b on compare match when up-counting. set oc2b on compare match when down-counting. 11 set oc2b on compare match when up-counting. clear oc2b on compare match when down-counting. table 18-8. waveform generation mode bit description mode wgm22 wgm21 wgm20 timer/counter mode of operation top update of ocrx at tov flag set on (1)(2) 0 0 0 0 normal 0xff immediate max 1001 pwm, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 3 0 1 1 fast pwm 0xff bottom max 4100reserved ? ? ? 5101 pwm, phase correct ocra top bottom 6110reserved ? ? ? 7111fast pwm ocrabottomtop 158 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 18.11.2 tccr2b ? timer/counter control register b ? bit 7 ? foc2a: force output compare a the foc2a bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring co mpatibility with future devices, this bit must be set to zero when tccr2b is written when operating in pwm mode. when writing a logical one to the foc2a bit, an immediate compare match is forced on the waveform generation unit. the oc2a output is changed according to its com2a1:0 bits setting. note that the foc2a bit is implemented as a strobe. therefore it is the value present in the com2a1:0 bits that determines the effect of the forced compare. a foc2a strobe will not generate any interrupt, nor will it clear the time r in ctc mode using ocr2a as top. the foc2a bit is always read as zero. ? bit 6 ? foc2b: force output compare b the foc2b bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring co mpatibility with future devices, this bit must be set to zero when tccr2b is written when operating in pwm mode. when writing a logical one to the foc2b bit, an immediate compare match is forced on the waveform generation unit. the oc2b output is changed according to its com2b1:0 bits setting. note that the foc2b bit is implemented as a strobe. therefore it is the value present in the com2b1:0 bits that determines the effect of the forced compare. a foc2b strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr2b as top. the foc2b bit is always read as zero. ? bits 5:4 ? reserved these bits are reserved bits in the atmega48a/pa/88a/pa/168a/pa/32 8/p and will always read as zero. ? bit 3 ? wgm22: waveform generation mode see the description in the ?tccr2a ? timer/counter contro l register a? on page 155 . ? bit 2:0 ? cs22:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see table 18-9 on page 158 . bit 7 6 5 4 3 2 1 0 (0xb1) foc2a foc2b ? ? wgm22 cs22 cs21 cs20 tccr2b read/write w w r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 18-9. clock select bit description cs22 cs21 cs20 description 0 0 0 no clock source (timer/counter stopped). 001clk t2s /(no prescaling) 010clk t2s /8 (from prescaler) 011clk t2s /32 (from prescaler) 100clk t2s /64 (from prescaler) 159 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 if external pin modes are used for the timer/counter0, transitions on the t0 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 18.11.3 tcnt2 ? timer/counter register the timer/counter register gives direct access, both for re ad and write operations, to the timer/counter unit 8-bit counter. writing to the tcnt2 register blocks (removes) the compare match on the following timer clock. modify- ing the counter (tcnt2) while the counter is running, introduces a risk of missing a compare match between tcnt2 and the ocr2x registers. 18.11.4 ocr2a ? output compare register a the output compare register a contains an 8-bit value that is continuously compared with the counter value (tcnt2). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc2a pin. 18.11.5 ocr2b ? output compare register b the output compare register b contains an 8-bit value that is continuously compared with the counter value (tcnt2). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc2b pin. 18.11.6 timsk2 ? timer/counter2 interrupt mask register ? bit 2 ? ocie2b: timer/counter2 output compare match b interrupt enable when the ocie2b bit is written to one and the i-bit in the status register is set (one), the timer/counter2 com- pare match b interrupt is enabled. the corresponding inte rrupt is executed if a compare match in timer/counter2 occurs, i.e., when the ocf2b bit is set in the timer/counter 2 interrupt flag register ? tifr2. 101clk t2s /128 (from prescaler) 110clk t 2 s /256 (from prescaler) 111clk t 2 s /1024 (from prescaler) table 18-9. clock select bit description cs22 cs21 cs20 description bit 76543210 (0xb2) tcnt2[7:0] tcnt2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0xb3) ocr2a[7:0] ocr2a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0xb4) ocr2b[7:0] ocr2b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543 2 1 0 (0x70) ?????ocie2bocie2atoie2timsk2 read/write rrrrr r/wr/wr/w initial value 00000 0 0 0 160 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bit 1 ? ocie2a: timer/counter2 output compare match a interrupt enable when the ocie2a bit is written to one and the i-bit in the status register is set (one), the timer/counter2 com- pare match a interrupt is enabled. the corresponding inte rrupt is executed if a compare match in timer/counter2 occurs, i.e., when the ocf2a bit is set in the timer/counter 2 interrupt flag register ? tifr2. ? bit 0 ? toie2: timer/counter2 overflow interrupt enable when the toie2 bit is written to one and the i-bit in the status register is set (one), the timer/counter2 overflow interrupt is enabled. the corresponding interrupt is executed if an overflow in timer/counter2 occurs, i.e., when the tov2 bit is set in the timer/counter2 interrupt flag register ? tifr2. 18.11.7 tifr2 ? timer/counter2 interrupt flag register ? bit 2 ? ocf2b: output compare flag 2 b the ocf2b bit is set (one) when a compare match occurs between the timer/counter2 and the data in ocr2b ? output compare register2. ocf2b is cleared by hardw are when executing the corresponding interrupt handling vector. alternatively, ocf2b is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie2b (timer/counter2 compare match interrupt enable), and ocf2b are set (one), the timer/counter2 compare match interrupt is executed. ? bit 1 ? ocf2a: output compare flag 2 a the ocf2a bit is set (one) when a compare match occurs between the timer/counter2 and the data in ocr2a ? output compare register2. ocf2a is cleared by hardw are when executing the corresponding interrupt handling vector. alternatively, ocf2a is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie2a (timer/counter2 compare match interrupt enable), and ocf2a are set (one), the timer/counter2 compare match interrupt is executed. ? bit 0 ? tov2: timer/counter2 overflow flag the tov2 bit is set (one) when an overflow occurs in ti mer/counter2. tov2 is cleared by hardware when execut- ing the corresponding interrupt handling vector. alternativel y, tov2 is cleared by writing a logic one to the flag. when the sreg i-bit, toie2a (timer/counter2 overflow interrupt enable), and tov2 are set (one), the timer/counter2 overflow interrupt is executed. in pwm mode, this bit is set when timer/counter2 changes count- ing direction at 0x00. 18.11.8 assr ? asynchronous status register ? bit 7 ? reserved this bit is reserved and will always read as zero. ? bit 6 ? exclk: enable external clock input when exclk is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be in put on timer oscillator 1 (tosc1) pin inst ead of a 32khz crystal. writing to exclk should be done before asynchronous operation is selected. no te that the crystal oscillator will only run when this bit is zero. bit 76543210 0x17 (0x37) ? ? ? ? ? ocf2b ocf2a tov2 tifr2 read/write r r r r r r/w r/w r/w initial value00000000 bit 7 6 5 4 3 2 1 0 (0xb6) ? exclk as2 tcn2ub ocr2aub ocr2bub tcr2aub tcr2bub assr read/write r r/w r/w r r r r r initial value 0 0 0 0 0 0 0 0 161 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bit 5 ? as2: asynchronous timer/counter2 when as2 is written to zero, timer/count er2 is clocked from the i/o clock, clk i/o . when as2 is written to one, timer/counter2 is clocked from a cr ystal oscillator connected to the timer oscillator 1 (tosc1) pin. when the value of as2 is changed, the contents of tcnt2, oc r2a, ocr2b, tccr2a and tccr2b might be corrupted. ? bit 4 ? tcn2ub: timer/counter2 update busy when timer/counter2 operates asynchronously and tcnt2 is written, this bit becomes set. when tcnt2 has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that tcnt2 is ready to be updated with a new value. ? bit 3 ? ocr2aub: output co mpare register2 update busy when timer/counter2 operates asynchronously and ocr2 a is written, this bit becomes set. when ocr2a has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that ocr2a is ready to be updated with a new value. ? bit 2 ? ocr2bub: output compare register2 update busy when timer/counter2 operates asynchronously and ocr2 b is written, this bit becomes set. when ocr2b has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that ocr2b is ready to be updated with a new value. ? bit 1 ? tcr2aub: timer/counter control register2 update busy when timer/counter2 operates asynchronously and tccr2a is written, this bit becomes se t. when tccr2a has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that tccr2a is ready to be updated with a new value. ? bit 0 ? tcr2bub: timer/counter control register2 update busy when timer/counter2 operates asynchronously and tccr2b is written, this bit becomes se t. when tccr2b has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that tccr2b is ready to be updated with a new value. if a write is performed to any of the five timer/c ounter2 registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. the mechanisms for reading tcnt2, ocr2a, ocr2 b, tccr2a and tccr2b are different. when reading tcnt2, the actual timer value is read. when readi ng ocr2a, ocr2b, tccr2a and tccr2b the value in the temporary storage register is read. 18.11.9 gtccr ? general time r/counter control register ? bit 1 ? psrasy: prescaler reset timer/counter2 when this bit is one, the timer/counter2 prescaler will be re set. this bit is normally cleared immediately by hard- ware. if the bit is writte n when timer/counter2 is operating in asynch ronous mode, t he bit will remain one until the prescaler has been reset. the bit will not be cleared by hardware if the tsm bit is set. refer to the description of the ?bit 7 ? tsm: timer/counter synchronization mode? on page 141 for a description of the timer/counter syn- chronization mode. bit 7 6 5 4 3 2 1 0 0x23 (0x43) tsm ? ? ? ? ? psrasy psrsync gtccr read/write r/w r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 162 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 19. spi ? serial peripheral interface 19.1 features ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? seven programmable bit rates ? end of transmission interrupt flag ? write collision flag protection ? wake-up from idle mode ? double speed (ck/2) master spi mode 19.2 overview the serial peripheral interface (spi) allows high-speed synchronous data transfer between the atmega48a/pa/88a/pa/168a/pa/328/p and peripheral devices or between several avr devices. the usart can also be used in master spi mode, see ?usart in spi mode? on page 199 . the prspi bit in ?min- imizing power consum ption? on page 41 must be written to zero to enable spi module. figure 19-1. spi block diagram (1) note: 1. refer to figure 1-1 on page 2 , and table 14-3 on page 83 for spi pin placement. the interconnection between master and slave cpus with spi is shown in figure 19-2 on page 163 . the system consists of two shift registers, and a master clock generator. the spi master initiates the communication cycle spi2x spi2x divider /2/4/8/16/32/64/128 163 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 when pulling low the slave select ss pin of the desired slave. master and slave prepare the data to be sent in their respective shift registers, and the master generates the required clock pulses on the sck line to interchange data. data is always shifted from master to slave on the master out ? slave in, mosi, line, and from slave to mas- ter on the master in ? slave out, miso, line. after eac h data packet, the master will synchronize the slave by pulling high the slave select, ss , line. when configured as a master, the spi interface has no automatic control of the ss line. this must be handled by user software before communication can start. when this is done, writing a byte to the spi data register starts the spi clock generator, and the hardware shifts the eight bits into the slave. after shifting one byte, the spi clock gen- erator stops, setting the end of transmission flag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrupt is requested. the master may continue to shift the next byte by writing it into spdr, or signal the end of packet by pulling high the slave select, ss line. the last inco ming byte will be kept in the buffer register for later use. when configured as a slave, the spi interface will remain sleeping with mi so tri-stated as long as the ss pin is driven high. in this state, software may update the cont ents of the spi data register, spdr, but the data will not be shifted out by incoming clock pulses on the sck pin until the ss pin is driven low. as one byte has been com- pletely shifted, the end of transmission flag, spif is set. if the spi interrupt enable bit, spie, in the spcr register is set, an interrupt is requested. the slave ma y continue to place new data to be sent into spdr before reading the incoming data. the la st incoming byte will be kept in the buffer register for later use. figure 19-2. spi master-slave interconnection the system is single buffered in the transmit direction and double buffered in the receive direction. this means that bytes to be transmitted cannot be written to the spi data register before the entire shift cycle is completed. when receiving data, however, a received character must be read from the spi data register before the next character has been completely shifted in. otherwise, the first byte is lost. in spi slave mode, the control logic w ill sample the incoming si gnal of the sck pin. to ensure correc t sampling of the clock signal, the minimum low and high periods should be: low periods: longer than 2 cpu clock cycles. high periods: longer than 2 cpu clock cycles. shift enable 164 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 when the spi is enabled, the data direction of the mosi, miso, sck, and ss pins is overridden according to table 19-1 on page 164 . for more details on automatic port overrides, refer to ?alternate port functions? on page 81 . note: see ?alternate functions of port b? on page 83 for a detailed description of how to define the direction of the user defined spi pins. the following code examples show how to initialize the spi as a master and how to perform a simple transmission. ddr_spi in the examples must be re placed by the actual data directio n register controlling the spi pins. dd_mosi, dd_miso and dd_sck must be replaced by the actu al data direction bits for these pins. e.g. if mosi is placed on pin pb5, replace dd_mo si with ddb5 and ddr_spi with ddrb. table 19-1. spi pin overrides (note:) pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input 165 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. see ?about code examples? on page 7. assembly code example (1) spi_masterinit: ; set mosi and sck output, all others input ldi r17,(1< 168 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 19-3. spi transfer format with cpha = 0 figure 19-4. spi transfer format with cpha = 1 bit 1 bit 6 l s b m s b s ck (cpol = 0) mode 0 s ample i mo s i/mi s o change 0 mo s i pin change 0 mi s o pin s ck (cpol = 1) mode 2 ss m s b l s b bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 m s b fir s t (dord = 0) l s b fir s t (dord = 1) s ck (cpol = 0) mode 1 s ample i mo s i/mi s o change 0 mo s i pin change 0 mi s o pin s ck (cpol = 1) mode 3 ss m s b l s b bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 l s b m s b m s b fir s t (dord = 0) l s b fir s t (dord = 1) 169 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 19.5 register description 19.5.1 spcr ? spi control register ? bit 7 ? spie: spi interrupt enable this bit causes the spi interr upt to be exec uted if spif bit in the spsr register is set and the if the global inter- rupt enable bit in sreg is set. ? bit 6 ? spe: spi enable when the spe bit is written to one, the spi is enabled. this bit must be set to enable any spi operations. ? bit 5 ? dord: data order when the dord bit is written to one, the lsb of the data word is transmitted first. when the dord bit is written to zero, the msb of the data word is transmitted first. ? bit 4 ? mstr: master/slave select this bit selects master spi mode when written to one, and slave spi mode when written logic zero. if ss is config- ured as an input and is driven low while mstr is se t, mstr will be cleared, and sp if in spsr will become set. the user will then have to set mstr to re-enable spi master mode. ? bit 3 ? cpol: clock polarity when this bit is written to one, sck is high when idle. when cpol is written to zero, sck is low when idle. refer to figure 19-3 and figure 19-4 for an example. the cpol functionality is summarized below: ? bit 2 ? cpha: clock phase the settings of the clock phase bit (cpha) determine if data is sampled on the leading (first) or trailing (last) edge of sck. refer to figure 19-3 and figure 19-4 for an example. the cpol functionality is summarized below: ? bits 1, 0 ? spr1, spr0: spi clock rate select 1 and 0 these two bits control the sck rate of the device confi gured as a master. spr1 and spr0 have no effect on the slave. the relationship between sck and the oscillator clock frequency f osc is shown in the following table: bit 76543210 0x2c (0x4c) spie spe dord mstr cpol cpha spr1 spr0 spcr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 19-3. cpol functionality cpol leading edge trailing edge 0 rising falling 1 falling rising table 19-4. cpha functionality cpha leading edge trailing edge 0 sample setup 1 setup sample 170 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 19.5.2 spsr ? spi status register ? bit 7 ? spif: spi interrupt flag when a serial transfer is complete, the spif flag is set. an interrupt is generated if spie in spcr is set and global interrupts are enabled. if ss is an input and is driven lo w when the spi is in master m ode, this will also set the spif flag. spif is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, the spif bit is cleared by first reading the spi status regist er with spif set, then accessing the spi data register (spdr). ? bit 6 ? wcol: write collision flag the wcol bit is set if the spi data register (spdr) is written during a data transfer. the wcol bit (and the spif bit) are cleared by first reading the spi status register with wcol set, and then accessing the spi data register. ? bit [5:1] ? reserved these bits are reserved bits in the atmega48a/pa/88a/pa/168a/pa/32 8/p and will always read as zero. ? bit 0 ? spi2x: double spi speed bit when this bit is written logic one the spi speed (sck frequency) will be doubled when the spi is in master mode (see table 19-5 ). this means that the minimum sck period will be two cpu clock periods. when the spi is config- ured as slave, the spi is only guaranteed to work at f osc /4 or lower. the spi interface on the atmega48a/ pa/88a/pa/168a/pa/328/p is also used for program memory and eeprom downloading or uploading. see page 299 for serial programming and verification. table 19-5. relationship between sck and the oscillator frequency spi2x spr1 spr0 sck frequency 000 f osc / 4 001 f osc / 16 010 f osc / 64 011 f osc / 128 100 f osc / 2 101 f osc / 8 110 f osc / 32 111 f osc / 64 bit 76543210 0x2d (0x4d) spif wcol ? ? ? ? ? spi2x spsr read/write rrrrrrrr/w initial value 0 0 0 0 0 0 0 0 171 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 19.5.3 spdr ? spi data register the spi data register is a read/write register used for data transfer between the register file and the spi shift register. writing to the register initiates data transmission . reading the register causes the shift register receive buffer to be read. bit 76543210 0x2e (0x4e) msb lsb spdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial valuexxxxxxxxu ndefined 172 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 20. usart0 20.1 features ? full duplex operation (independent se rial receive and transmit registers) ? asynchronous or synchronous operation ? master or slave clocked synchronous operation ? high resolution baud rate generator ? supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits ? odd or even parity generation and parity check supported by hardware ? data overrun detection ? framing error detection ? noise filtering includes false start bi t detection and digital low pass filter ? three separate interrupts on tx complete , tx data register empty and rx complete ? multi-processor communication mode ? double speed asynchronous communication mode 20.2 overview the universal synchronous and asynchronous serial receiv er and transmitter (usart) is a highly flexible serial communication device. the usart0 can also be used in master spi mode, see ?usart in spi mode? on page 199 . the power reduc- tion usart bit, prusart0, in ?minimizing power consumption? on page 41 must be disabled by writing a logical zero to it. a simplified block diagram of the usart transmitter is shown in figure 20-1 on page 173 . cpu accessible i/o registers and i/o pins are shown in bold. the dashed boxes in the block diagram separate the three main parts of the usart (listed from the top): clock generator, transmitter and receiver. control registers are shared by all units. the clock generation logic con- sists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. the xckn (transfer clock) pin is only used by synchronous transfer mode. the transmitter consists of a single write buffer, a serial shift register, parity generator and control logic for handling different serial frame formats. the write buffer allows a continuous transfer of data without any delay between frames. the receiver is the most complex part of the usart module due to its clock and data recovery units. the recovery units are used for asynchronous data reception. in addition to the recovery units, the receiver includes a parity checker, control logic, a shift register and a two level receive buffer (udrn). the receiver supports the same frame formats as the transmitter, and can detect frame error, data overrun and parity errors. 173 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 20-1. usart block diagram (1) note: 1. refer to figure 1-1 on page 2 and table 14-9 on page 89 for usart0 pin placement. 20.3 clock generation the clock generation logic generates the base clock for the transmitter and receiver. the usart supports four modes of clock operation: normal asynchronous, double speed asynchronous, master synchronous and slave synchronous mode. the umseln bit in usart control and status register c (ucsrn c) selects between asyn- chronous and synchronous operation. double speed (asynchronous mode only) is controlled by the u2xn found in the ucsrna register. when using synchronous mode (umseln = 1), the data direction register for the xckn pin (ddr_xckn) controls whether the clo ck source is internal (master mode) or external (slave mode). the xckn pin is only active when using synchronous mode. parity generator ubrrn [h:l] udr n(transmit) ucsrna ucsrnb ucsrnc baud rate generator transmit shift register receive shift register rxdn txdn pin control udrn (receive) pin control xckn data recovery clock recovery pin control tx control rx control parity checker data bus osc sync logic clock generator transmitter receiver 174 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 20-2 shows a block diagram of the clock generation logic. figure 20-2. clock generation logic, block diagram signal description: txclk transmitter clock (internal signal). rxclk receiver base clock (internal signal). xcki input from xck pin (internal signal). used for synchronous slave operation. xcko clock output to xck pin (internal signal). used for synchronous master operation. fosc system clock frequency. 20.3.1 internal clock generation ? the baud rate generator internal clock generation is used for the asynchronous and the synchronous master modes of operation. the description in this section refers to figure 20-2 . the usart baud rate register (ubrrn) and the down-count er connected to it function as a programmable pres- caler or baud rate generator. the down-counter, running at system clock (f osc ), is loaded with the ubrrn value each time the counter has counted down to zero or when the ubrrnl register is written. a clock is generated each time the counter reaches zero. this clock is the baud rate generator clock output (= f osc /(ubrrn+1)). the transmitter divides the baud rate generator clock output by 2, 8 or 16 depending on mode. the baud rate genera- tor output is used directly by the receiver?s clock and data recovery units. however, the recovery units use a state machine that uses 2, 8 or 16 states depending on mo de set by the state of the umseln, u2xn and ddr_xckn bits. prescaling down-counter /2 ubrrn /4 /2 foscn ubrrn+1 sync register osc xckn pin txclk u2xn umseln ddr_xckn 0 1 0 1 xcki xcko ddr_xckn rxclk 0 1 1 0 edge detector ucpoln 175 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 table 20-1 contains equations for calculating the baud rate (i n bits per second) and for calculating the ubrrn value for each mode of operation using an internally generated clock source. note: 1. the baud rate is defined to be the transfer rate in bit per second (bps) baud baud rate (in bits per second, bps) f osc system oscillator clock frequency ubrrn contents of the ubrrnh and ubrrnl registers, (0-4095) some examples of ubrrn values for some system clock frequencies are found in table 20-4 (see page 190 ). 20.3.2 double speed operation (u2xn) the transfer rate can be doubled by setting the u2xn bit in ucsrna. setting this bit only has effect for the asyn- chronous operation. set this bit to zero when using synchronous operation. setting this bit will reduce the divisor of the baud rate divider from 16 to 8, e ffectively doubling the transfer rate for asynchronous communication. note however that the receiver will in this case only use half the number of sam- ples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used. for the transmitter, there are no downsides. 20.3.3 external clock external clocking is used by the sync hronous slave modes of operation. the description in this section refers to figure 20-2 for details. table 20-1. equations for calculating baud rate register setting operating mode equation for calculating baud rate (1) equation for calculating ubrrn value asynchronous normal mode (u2xn = 0) asynchronous double speed mode (u2xn = 1) synchronous master mode baud f osc 16 ubrr n 1 + ?? ----------------------------------------- - = ubrr n f osc 16 baud ----------------------- - 1 ? = baud f osc 8 ubrr n 1 + ?? -------------------------------------- - = ubrr n f osc 8 baud -------------------- 1 ? = baud f osc 2 ubrr n 1 + ?? -------------------------------------- - = ubrr n f osc 2 baud -------------------- 1 ? = 176 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 external clock input from the xckn pin is sampled by a synchronization register to minimize the chance of meta- stability. the output from the synchr onization register must then pass through an edge detector before it can be used by the transmitter and receiver. this process in troduces a two cpu clock period delay and therefore the maximum external xckn clock frequenc y is limited by the following equation: note that f osc depends on the stab ility of the system clock so urce. it is therefore recomm ended to add some margin to avoid possible loss of data due to frequency variations. 20.3.4 synchronous clock operation when synchronous mode is used (umseln = 1), the xckn pin will be used as either clock input (slave) or clock output (master). the dependency between the clock edges and data sampling or data change is the same. the basic principle is that data input (on rxdn) is sampled at the opposite xckn clock edge of the edge the data output (txdn) is changed. figure 20-3. synchronous mode xckn timing. the ucpoln bit ucrsc selects which xckn clock edge is used for data sampling and which is used for data change. as figure 20-3 shows, when ucpoln is zero the data will be changed at rising xckn edge and sampled at falling xckn edge. if ucpoln is se t, the data will be changed at falling xckn edge a nd sampled at rising xckn edge. 20.4 frame formats a serial frame is defined to be one character of data bits wi th synchronization bits (start and stop bits), and option- ally a parity bit for error checking. the usart accepts all 30 combinations of the following as valid frame formats: ? 1 start bit ? 5, 6, 7, 8, or 9 data bits ? no, even or odd parity bit ? 1 or 2 stop bits a frame starts with the start bit followed by the least si gnificant data bit. then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit. if enabled, the pari ty bit is inserted after the data bits, before the stop bits. when a complete frame is transmitt ed, it can be directly followed by a new frame, or the com- munication line can be set to an idle (high) state. figure 20-4 illustrates the possible combinations of the frame formats. bits inside brackets are optional. f xck f osc 4 ----------- ? rxd / txd xck rxd / txd xck ucpol = 0 ucpol = 1 sample sample 177 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 20-4. frame formats st start bit, always low. (n) data bits (0 to 8). p parity bit. can be odd or even. sp stop bit, always high. idle no transfers on the communication line (rxdn or txdn). an idle line must be high. the frame format used by the usart is set by the ucszn2:0, upmn1:0 and usbsn bits in ucsrnb and ucs- rnc. the receiver and transmitter use the same setting. note that changing the setting of any of these bits will corrupt all ongoing communication for both the receiver and transmitter. the usart character size (ucszn2:0) bits select the number of data bits in the frame. the usart parity mode (upmn1:0) bits enable and set the type of parity bit. the selection between one or two stop bits is done by the usart stop bit select (usbsn) bit. the receiver ignores the seco nd stop bit. an fe (frame error) will therefore only be detected in the cases where the first stop bit is zero. 20.4.1 parity bit calculation the parity bit is calculated by doing an ex clusive-or of all the data bits. if odd parity is used, the result of the exclu- sive or is inverted. the relation between the parity bit and data bits is as follows: p even parity bit using even parity p odd parity bit using odd parity d n data bit n of the character if used, the parity bit is located between the last data bit and first stop bit of a serial frame. 20.5 usart initialization the usart has to be initialized before any communication can take place. the initialization process normally con- sists of setting the baud rate, setting frame format and enabling the transmitter or the receiver depending on the usage. for interrupt driven usart operation, the global interrupt flag should be cleared (and interrupts globally disabled) when doing the initialization. before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmis- sions during the period the registers are changed. the tx cn flag can be used to check that the transmitter has completed all transfers, and the rxc flag can be used to check that there are no unread data in the receive buffer. note that the txcn flag must be cleared before each transmission (before udrn is written) if it is used for this purpose. 1 0 2 3 4 [5] [6] [7] [8] [p] st sp1 [sp2] (st / idle) (idle) frame p even d n 1 ? ? d 3 d 2 d 1 d 0 0 p odd ?????? d n 1 ? ? d 3 d 2 d 1 d 0 1 ?????? = = 178 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 the following simple usart initializat ion code examples show one assembly and one c function that are equal in functionality. the examples assume asynchronous oper ation using polling (no interr upts enabled) and a fixed frame format. the baud rate is given as a function parameter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. note: 1. see ?about code examples? on page 7. more advanced initialization routines can be made that include frame format as parameters, disable interrupts and so on. however, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine, or be co mbined with initialization code for other i/o modules. assembly code example (1) usart_init: ; set baud rate out ubrrnh, r17 out ubrrnl, r16 ; enable receiver and transmitter ldi r16, (1< 182 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. see ?about code examples? on page 7. for i/o registers located in extended i/ o map, ?in?, ?out?, ?sbis?, ?sbic?, ?c bi?, and ?sbi? instructions must be replaced with instructions that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. the function simply waits for data to be present in the receive buffer by checking the rxcn flag, before reading the buffer and returning the value. 20.7.2 receiving frames with 9 data bits if 9-bit characters are used (ucszn=7) the ninth bit must be read from the rxb8n bit in ucsrnb before reading the low bits from the udrn. this rule applies to the fen, dorn and upen status flags as well. read status from ucsrna, then data from udrn . reading the udrn i/o loca tion will change the state of the receive buffer fifo and consequently the txb8n, fen, dorn and upen bits, which all are stored in the fifo, will change. the following code example shows a simple usart receive function that handles both nine bit characters and the status bits. assembly code example (1) usart_receive: ; wait for data to be received in r16, ucsrna sbrs r16, udren rjmp usart_receive ; get and return received data from buffer in r16, udrn ret c code example (1) unsigned char usart_receive( void ) { /* wait for data to be received */ while ( !(ucsrna & (1< 184 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 20.7.3 receive compete flag and interrupt the usart receiver has one flag that indicates the receiver state. the receive complete (rxcn) flag indicates if there are un read data present in the receive buffer. this flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disabled (rxenn = 0) , the receive buffer will be flushed and consequently the rxcn bit will become zero. when the receive complete interrupt enable (rxcien) in ucsrnb is set, the usart re ceive complete interrupt will be executed as long as the rxcn flag is set (p rovided that global interrupts are enabled). when interrupt- driven data reception is used, the receive complete routine must read the received data from udrn in order to clear the rxcn flag, othe rwise a new interrupt w ill occur once the interr upt routine terminates. 20.7.4 receiver error flags the usart receiver has three error flags: frame error (fen), data overrun (dorn) and parity error (upen). all can be accessed by reading ucsrna. common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. due to the buffering of the error flags, the ucs- rna must be read before the receive buffer (udrn), since reading the udrn i/o location changes the buffer read location. another equality for the error flags is that they can not be altered by software doing a write to the flag location. however, all flags must be set to zero when the ucsrna is written for upward compatibility of future usart implementations. none of the error flags can generate interrupts. the frame error (fen) flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. the fen flag is zero when t he stop bit was correctly read (as one), and the fen flag will be one when the stop bit was incorrect (zero). this flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. the fen flag is not affected by the setting of the usbsn bit in ucsrnc since the receiver ignores all, except for the first, stop bits. for compatib ility with future devices, always se t this bit to zero when writ- ing to ucsrna. the data overrun (dorn) flag indicates data loss due to a receiver buffer full condition. a data overrun occurs when the receive buffer is full (two ch aracters), it is a new character waitin g in the receive shift register, and a new start bit is detected. if the dorn flag is set there was one or more serial frame lost between the frame last read from udrn, and the next frame re ad from udrn. for compatibility with futu re devices, always write this bit to zero when writing to ucsrna. the dorn flag is cleared when the frame received was successfully moved from the shift register to the receive buffer. the parity error (upen) flag indicates that the next frame in the receive buffer had a parity error when received. if parity check is not enabled the upen bit will always be read zero. for compatibility with fu ture devices, always set this bit to zero when writing to ucsrna. for more details see ?parity bit calculation? on page 177 and ?parity checker? on page 184 . 20.7.5 parity checker the parity checker is active when the high usart parity mode (upmn1) bit is set. type of parity check to be per- formed (odd or even) is selected by the upmn0 bit. when en abled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. the result of the check is stored in the receive buffer together with the received data and stop bits. the parity error (upen) flag can then be read by software to check if the frame had a parity error. the upen bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (upmn1 = 1). this bit is valid until the receive buffer (udrn) is read. 185 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 20.7.6 disabling the receiver in contrast to the transmitter, disab ling of the receiver will be immediate. data from on going receptions will there- fore be lost. when disa bled (i.e., the rxenn is set to zero) the rece iver will no longer override the normal function of the rxdn port pin. the receiver buffer fifo will be flushed when the receiver is disabled. remaining data in the buffer will be lost 20.7.7 flushing the receive buffer the receiver buffer fifo wil l be flushed when the receiv er is disabled, i.e., the bu ffer will be emptied of its con- tents. unread data will be lost. if the buffer has to be flushed during normal operation, due to for instance an error condition, read the udrn i/o location until the rxcn flag is cleared. the following code example shows how to flush the receive buffer. note: 1. see ?about code examples? on page 7. for i/o registers located in extended i/ o map, ?in?, ?out?, ?sbis?, ?sbic?, ?c bi?, and ?sbi? instructions must be replaced with instructions that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. 20.8 asynchronous data reception the usart includes a clock recovery and a data recovery unit for handling asynchronous data reception. the clock recovery logic is used for synchronizing the interna lly generated baud rate clo ck to the incoming asynchro- nous serial frames at the rxdn pin. the data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the receiver. the asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. 20.8.1 asynchronous clock recovery the clock recovery logic sync hronizes internal clock to the incoming serial frames. figure 20-5 illustrates the sam- pling process of the start bit of an incoming frame. the sample rate is 16 times the baud rate for normal mode, and eight times the baud rate for double speed mode. the horiz ontal arrows illustrate the synchronization variation due to the sampling process. note the larger time va riation when using the double speed mode (u2xn = 1) of operation. samples denoted zero are samples done when the rxdn line is idle (i.e., no communication activity). assembly code example (1) usart_flush: in r16, ucsrna sbrs r16, rxcn ret in r16, udrn rjmp usart_flush c code example (1) void usart_flush( void ) { unsigned char dummy; while ( ucsrna & (1< 187 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 the same majority voting is done to the stop bit as done for the other bits in the frame. if the stop bit is registered to have a logic 0 value, the fr ame error (fen) flag will be set. a new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. for normal speed mode, the first low level sample can be at point marked (a) in figure 20-7 . for double speed mode the first low level must be delayed to (b). (c) marks a stop bit of full length. the early start bit detection influences the operational range of the receiver. 20.8.3 asynchronous operational range the operational range of the receiver is dependent on the mismatch between the received bit rate and the inter- nally generated baud rate. if the transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the receiver does not have a similar (see table 20-2 on page 187 ) base frequency, the receiver will not be able to synchr onize the frames to the start bit. the following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. d sum of character size and parity size (d = 5 to 10 bit) s samples per bit. s = 16 for normal speed mode and s = 8 for double speed mode. s f first sample number used for majority voting. s f = 8 for normal speed and s f = 4 for double speed mode. s m middle sample number used for majority voting. s m = 9 for normal speed and s m = 5 for double speed mode. r slow is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate. r fast is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate. table 20-2 on page 187 and table 20-3 on page 188 list the maximum receiver baud rate error that can be toler- ated. note that normal speed mode has higher toleration of baud rate variations. table 1. table 20-2. recommended maximum receiver baud rate error for normal speed mode (u2xn = 0) d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 93.20 106.67 +6.67/-6.8 3.0 6 94.12 105.79 +5.79/-5.88 2.5 7 94.81 105.11 +5.11/-5.19 2.0 8 95.36 104.58 +4.58/-4.54 2.0 9 95.81 104.14 +4.14/-4.19 1.5 10 96.17 103.78 +3.78/-3.83 1.5 r slow d 1 + ?? s s 1 ? ds ? s f ++ ------------------------------------------ - = r fast d 2 + ?? s d 1 + ?? ss m + ----------------------------------- = 188 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 the recommendations of the maximum receiver baud rate error was made under the assumption that the receiver and transmitter equally divides the maximum total error. there are two possible sources for the receivers baud rate error. the receiver?s system clock (xtal) will always have some minor instability over the supply voltage range and th e temperature range. when using a crystal to gen- erate the system clock, this is rare ly a problem, but for a resonator the system clock may differ more than 2% depending of the resonators tolerance. the second source for the error is more controllable. the baud rate gener- ator can not always do an exact division of the system fr equency to get the baud rate wanted. in this case an ubrrn value that gives an acceptable low error can be used if possible. 20.9 multi-processor communication mode setting the multi-processor communication mode (mpcmn) bi t in ucsrna enables a filtering function of incoming frames received by the usart receiver. frames that do not contain address information will be ignored and not put into the receive buffer. this effectively reduces the number of incoming frames that has to be handled by the cpu, in a system with multiple mcus that communicate via the same serial bus. the transmitter is unaffected by the mpcmn setting, but has to be used differently when it is a part of a system utiliz ing the multi-processor com- munication mode. if the receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indicates if the frame contains data or address information. if the receiver is se t up for frames with nine data bits, then the ninth bit (rxb8n) is used for identifying address and data frames. when the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. when the frame type bit is zero the frame is a data frame. the multi-processor communication mode enables several slave mcus to receive data from a master mcu. this is done by first decoding an address frame to find out which mcu has been addressed. if a particular slave mcu has been addressed, it will re ceive the following data fram es as normal, while the ot her slave mcus will ignore the received frames until another address frame is received. 20.9.1 using mpcmn for an mcu to act as a master mcu, it can use a 9-bit character frame format (ucszn = 7). the ninth bit (txb8n) must be set when an address frame (txb8n = 1) or cleared when a data frame (txb = 0) is being transmitted. the slave mcus must in this case be set to use a 9-bit character frame format. the following procedure should be used to exchange data in multi-processor communication mode: 1. all slave mcus are in multi-proc essor communication mode (mpcmn in ucsrna is set). 2. the master mcu sends an address frame, and all slaves receive and read this frame. in the slave mcus, the rxcn flag in ucsrna will be set as normal. table 20-3. recommended maximum receiver baud rate error for double speed mode (u2xn = 1) d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 94.12 105.66 +5.66/-5.88 2.5 6 94.92 104.92 +4.92/-5.08 2.0 7 95.52 104,35 +4.35/-4.48 1.5 8 96.00 103.90 +3.90/-4.00 1.5 9 96.39 103.53 +3.53/-3.61 1.5 10 96.70 103.23 +3.23/-3.30 1.0 189 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 3. each slave mcu reads the udrn register and determines if it has been selected. if so, it clears the mpcmn bit in ucsrna, otherwise it waits for the next address byte and keeps the mpcmn setting. 4. the addressed mcu will receive all data frames until a new address fr ame is received. the other slave mcus, which still have the mpcmn bit set, will ignore t he data frames. 5. when the last data frame is received by the addressed mcu, the addressed mcu sets the mpcmn bit and waits for a new address frame from master. the process then repeats from 2. using any of the 5- to 8-bit character frame formats is possible, but impractical since the receiver must change between using n and n+1 character frame formats. this makes full-duplex operation difficult since the transmitter and receiver uses the same character size setting. if 5- to 8-bit character frames are used, the transmitter must be set to use two stop bit (usbsn = 1) since the fi rst stop bit is used for in dicating the frame type. do not use read-modify-write instructions (sbi and cbi) to set or clear the mpcmn bit. the mpcmn bit shares the same i/o location as the txcn flag and this might acci dentally be cleared when usin g sbi or cbi instructions. 20.10 examples of ba ud rate setting for standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the ubrrn settings in table 20-4 . ubrrn values which yield an actual baud rate differ- ing less than 0.5% from the target baud rate, are bold in the table. higher error ratings are acceptable, but the receiver will have less noise resistance when the error ratings are high , especially for large serial frames (see ?asynchronous operational range? on page 187 ). the error values are calculated using the following equation: error[%] baudrate closest match baudrate -------------------------------------------------- 1 ? ?? ?? 100 % ? = 190 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. ubrrn = 0, error = 0.0% table 20-4. examples of ubrrn settings for co mmonly used oscillator frequencies baud rate (bps) f osc = 1.0000mhz f osc = 1.8432mhz f osc = 2.0000mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 38.4k 1 -18.6% 2 8.5% 2 0. 0% 5 0.0% 2 8.5% 6 -7.0% 57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 76.8k ? ? 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5% 115.2k ? ? 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5% 230.4k??????00.0%???? 250k??????????00.0% max. (1) 62.5kbps 125kbps 115.2kbps 230.4kbps 125kbps 250kbps 191 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 table 20-5. examples of ubrrn settings for common ly used oscillator frequencies (continued) baud rate (bps) f osc = 3.6864mhz f osc = 4.0000mhz f osc = 7.3728mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 230.0%470.0%250.2%510.2%470.0%950.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0% 28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0% 38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0% 230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0% 250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8% 0.5m ? ? 0 -7.8% ? ? 0 0.0% 0 -7.8% 1 -7.8% 1m ??????????0-7.8% max. (1) 230.4kbps 460.8kbps 250kbps 0 .5mbps 460.8kbps 921.6kbps 1. ubrrn = 0, error = 0.0% 192 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 table 20-6. examples of ubrrn settings for common ly used oscillator frequencies (continued) baud rate (bps) f osc = 8.0000mhz f osc = 11.0592 mhz f osc = 14.7456mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.0% 95 0.0% 28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0% 38.4k 12 0.2% 25 0.2% 17 0.0% 35 0.0% 23 0.0% 47 0.0% 57.6k 8 -3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0% 76.8k 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0% 115.2k 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0% 230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0% 250k 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3% 0.5m 0 0.0% 1 0.0% ? ? 2 -7.8% 1 -7.8% 3 -7.8% 1m ??00.0%????0-7.8%1-7.8% max. (1) 0.5mbps 1mbps 691.2kbps 1.382 4mbps 921.6kbps 1.8432mbps 1. ubrrn = 0, error = 0.0% 193 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 table 20-7. examples of ubrrn settings for common ly used oscillator frequencies (continued) baud rate (bps) f osc = 16.0000mhz f osc = 18.4320mhz f osc = 20.0000mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2% 28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2% 38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 -1.4% 64 0.2% 57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1.4% 42 0.9% 76.8k 12 0.2% 25 0.2% 14 0.0% 29 0.0% 15 1.7% 32 -1.4% 115.2k 8 -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4% 230.4k 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4% 250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0% 0.5m 1 0.0% 3 0.0% ? ? 4 -7.8% ? ? 4 0.0% 1m 00.0%10.0%???????? max. (1) 1mbps 2mbps 1.152mbps 2. 304mbps 1.25mbps 2.5mbps 1. ubrrn = 0, error = 0.0% 194 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 20.11 register description 20.11.1 udrn ? usart i/o data register n the usart transmit data buffer register and usart rece ive data buffer registers share the same i/o address referred to as usart data register or udrn. the transmit data buffer regi ster (txb) will be the destination for data written to the udrn register location. reading the udrn register location will return the contents of the receive data buffer register (rxb). for 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the transmitter and set to zero by the receiver. the transmit buffer can only be written when the udren flag in the ucsrn a register is set. da ta written to udrn when the udren flag is not set, will be ignored by the usar t transmitter. when data is written to the transmit buffer, and the transmitter is enabled, the transmitter will load the data in to the transmit shif t register when the shift register is empty. th en the data will be serially transmitted on the txdn pin. the receive buffer consists of a tw o level fifo. the fifo will change its state whenever the receive buffer is accessed. due to this behavior of the receive buffer, do not use read-modify-write instructions (sbi and cbi) on this location. be careful when using bi t test instructions (sbic and sbis), si nce these also will change the state of the fifo. 20.11.2 ucsrna ? usart contro l and status register n a ? bit 7 ? rxcn: usart receive complete this flag bit is set when there are unread data in the re ceive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disabled, the receive buffer will be flushed and conse- quently the rxcn bit will become zero. th e rxcn flag can be used to genera te a receive comple te interrupt (see description of the rxcien bit). ? bit 6 ? txcn: usart transmit complete this flag bit is set when the entire frame in the transmit shift register has been shifted out and there are no new data currently present in th e transmit buffer (udrn). the txcn flag bit is automatica lly cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. the txcn flag can generate a transmit complete interrupt (see description of the txcien bit). ? bit 5 ? udren: usart data register empty the udren flag indicates if the transmit buffer (udrn) is ready to receive new data. if udren is one, the buffer is empty, and therefore ready to be written. the udren flag can generate a data register empty interrupt (see description of the udrien bit). udren is set after a reset to indicate that the transmitter is ready. bit 76543210 rxb[7:0] udrn (read) txb[7:0] udrn (write) read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 rxcn txcn udren fen dorn upen u2xn mpcmn ucsrna read/write r r/w r r r r r/w r/w initial value00100000 195 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bit 4 ? fen: frame error this bit is set if the next character in the receive buff er had a frame error when received. i.e., when the first stop bit of the next character in the receive buffer is zero. this bit is valid until the receive buffer (udrn) is read. the fen bit is zero when the stop bit of received data is one. always set this bit to zero when writing to ucsrna. ? bit 3 ? dorn: data overrun this bit is set if a data overrun condition is detected. a data overrun occurs when th e receive buffer is full (two characters), it is a new character wait ing in the receive shift register, and a new start bit is detected. this bit is valid until the receive buffer (udrn) is read. always set this bit to zero when writing to ucsrna. ? bit 2 ? upen: usart parity error this bit is set if the next character in the receive buf fer had a parity error when received and the parity checking was enabled at that point (upmn1 = 1). this bit is valid unt il the receive buffer (udrn) is read. always set this bit to zero when writing to ucsrna. ? bit 1 ? u2xn: double the usart transmission speed this bit only has effect for the asynchronous operation. write this bit to zero when using synchronous operation. writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 ef fectively doubling the transfer rate for asynchronous communication. ? bit 0 ? mpcmn: multi-processor communication mode this bit enables the multi-processor communication mode. when the mpcmn bit is written to one, all the incoming frames received by the usart receiver that do not contain addr ess information will be igno red. the transmitter is unaffected by the mpcmn setting. for more detailed information see ?multi-processor communication mode? on page 188 . 20.11.3 ucsrnb ? usart contro l and status register n b ? bit 7 ? rxcien: rx complete interrupt enable n writing this bit to one enables inte rrupt on the rxcn flag. a usart rece ive complete interrupt will be generated only if the rxcien bit is written to one, the global interrupt flag in sreg is written to one and the rxcn bit in ucsrna is set. ? bit 6 ? txcien: tx complete interrupt enable n writing this bit to one enab les interrupt on the txcn flag. a usart tr ansmit complete inte rrupt will be generated only if the txcien bit is written to one, the global interrup t flag in sreg is written to one and the txcn bit in ucs- rna is set. bit 76543210 rxcien txcien udrien rxenn txenn ucszn2 rxb8n txb8n ucsrnb read/write r/w r/w r/w r/w r/w r/w r r/w initial value 0 0 0 0 0 0 0 0 196 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bit 5 ? udrien: usart data register empty interrupt enable n writing this bit to one enables interr upt on the udren flag. a data regist er empty interrupt will be generated only if the udrien bit is written to one, the global interrupt flag in sreg is written to one and the udren bit in ucs- rna is set. ? bit 4 ? rxenn: receiver enable n writing this bit to one enables the usart receiver. the receiver will overri de normal port operation for the rxdn pin when enabled. di sabling the receiver will flus h the receive buffer invali dating the fen, dorn, and upen flags. ? bit 3 ? txenn: transmitter enable n writing this bit to one enabl es the usart transmitter. t he transmitter will override no rmal port operation for the txdn pin when enabled. the disabling of the transmitter (writing txenn to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the transmit shift register and transmit buffer reg- ister do not contain data to be transm itted. when disabled, the tr ansmitter will no longer override the txdn port. ? bit 2 ? ucszn2: character size n the ucszn2 bits combined with the ucszn1:0 bit in ucsrnc sets the number of data bits (character size) in a frame the receiver and transmitter use. ? bit 1 ? rxb8n: receive data bit 8 n rxb8n is the ninth data bit of the received character when operating with serial frames with nine data bits. must be read before reading the low bits from udrn. ? bit 0 ? txb8n: transmit data bit 8 n txb8n is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. must be written before wr iting the low bits to udrn. 20.11.4 ucsrnc ? usart contro l and status register n c ? bits 7:6 ? umseln1:0 usart mode select these bits select the mode of operation of the usartn as shown in table 20-8 . note: 1. see ?usart in spi mode? on page 199 for full description of the master spi mode (mspim) operation bit 7 6 5 4 3 2 1 0 umseln1 umseln0 upmn1 upmn0 usbs n ucszn1 ucszn0 ucpoln ucsrnc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 1 1 0 table 20-8. umseln bits settings umseln1 umseln0 mode 0 0 asynchronous usart 0 1 synchronous usart 1 0 (reserved) 1 1 master spi (mspim) (1) 197 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bits 5:4 ? upmn1:0: parity mode these bits enable and set type of parity generation and check. if enabl ed, the transmitter will automatically gener- ate and send the parity of the transmit ted data bits within each frame. the receiver will ge nerate a parity value for the incoming data and compare it to the upmn setting. if a mismatch is det ected, the upen flag in ucsrna will be set. ? bit 3 ? usbsn: stop bit select this bit selects the number of stop bits to be inserted by the transmitter. the receiver ignores this setting. ? bit 2:1 ? ucszn1:0: character size the ucszn1:0 bits combined with the ucszn2 bit in ucsrnb sets the number of data bits (character size) in a frame the receiver and transmitter use. ? bit 0 ? ucpoln: clock polarity this bit is used for synchronous mode only. write this bit to zero when asynchronous mode is used. the ucpoln bit sets the relationship between data output change and data input sample, and the synchronous clock (xckn). table 20-9. upmn bits settings upmn1 upmn0 parity mode 00disabled 01reserved 1 0 enabled, even parity 1 1 enabled, odd parity table 20-10. usbs bit settings usbsn stop bit(s) 01-bit 12-bit table 20-11. ucszn bits settings ucszn2 ucszn1 ucszn0 character size 0005-bit 0016-bit 0107-bit 0118-bit 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1119-bit 198 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 20.11.5 ubrrnl and ubrrnh ? usart baud rate registers ? bit 15:12 ? reserved these bits are reserved for future use. for compatibility with future devices, these bit must be written to zero when ubrrnh is written. ? bit 11:0 ? ubrr[11:0]: usart baud rate register this is a 12-bit register which contains the usart baud rate. the ubrrnh contains the four most significant bits, and the ubrrnl contains the eight leas t significant bits of the usart ba ud rate. ongoing transmissions by the transmitter and receiver will be corrupt ed if the baud rate is changed. writ ing ubrrnl will trigger an immediate update of the baud rate prescaler. table 20-12. ucpoln bit settings ucpoln transmitted data changed (output of txdn pin) received data sampled (input on rxdn pin) 0 rising xckn edge falling xckn edge 1 falling xckn edge rising xckn edge bit 151413121110 9 8 ? ? ? ? ubrrn[11:8] ubrrnh ubrrn[7:0] ubrrnl 76543210 read/write r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 00000000 199 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 21. usart in spi mode 21.1 features ? full duplex, three-wire synchronous data transfer ? master operation ? supports all four spi modes of operation (mode 0, 1, 2, and 3) ? lsb first or msb first data transfer (configurable data order) ? queued operation (double buffered) ? high resolution baud rate generator ? high speed operation (f xckmax = f ck /2) ? flexible interrupt generation 21.2 overview the universal synchronous and asynchronous serial receiver and transmitter (usart) can be set to a master spi compliant mode of operation. setting both umseln1:0 bits to one enables the usart in mspim logic. in this mode of operation the spi master control logic takes direct control over the usart resources. these resource s include the transmitter and receiver shift register and buffers, and the baud rate generator. the parity generator and checker, the data and clock recov- ery logic, and the rx and tx control logic is disabled. the usart rx and tx control logic is replaced by a common spi transfer control logic. however, the pin control logic and interrupt generation logic is identical in both modes of operation. the i/o register locations are the same in both modes. howe ver, some of the functionality of the control registers changes when using mspim. 21.3 clock generation the clock generation logic generates the base clock for the transmitter and receiver. for usart mspim mode of operation only internal clock generation (i.e. master operation) is supported. the data direction register for the xckn pin (ddr_xckn) must therefore be set to one (i.e. as output) for the usart in mspim to operate correctly. preferably the ddr_xckn should be set up before the us art in mspim is enabled (i .e. txenn and rxenn bit set to one). the internal clock generation used in mspim mode is identical to the usart synchronous master mode. the baud rate or ubrrn setting can therefore be calculated using the same equations, see table 21-1 : note: 1. the baud rate is defined to be the transfer rate in bit per second (bps) baud baud rate (in bits per second, bps) table 21-1. equations for calculating baud rate register setting operating mode equation for calculating baud rate (1) equation for calculating ubrrn value synchronous master mode baud f osc 2 ubrr n 1 + ?? -------------------------------------- - = ubrr n f osc 2 baud -------------------- 1 ? = 200 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 f osc system oscillator clock frequency ubrrn contents of the ubrrnh and ubrrnl registers, (0-4095) 21.4 spi data modes and timing there are four combinations of xckn (sck) phase and polar ity with respect to serial data, which are determined by control bits ucphan and ucpoln. the da ta transfer timing diagrams are shown in figure 21-1 . data bits are shifted out and latched in on opposite edges of the xckn si gnal, ensuring sufficient time for data signals to stabi- lize. the ucpoln and ucphan fu nctionality is summarized in table 21-2 . note that changing the setting of any of these bits will corrupt all ongoi ng communication for both th e receiver and transmitter. figure 21-1. ucphan and ucpoln data transfer timing diagrams. 21.5 frame formats a serial frame for the mspim is defined to be one character of 8 data bits. the usart in mspim mode has two valid frame formats: ? 8-bit data with msb first ? 8-bit data with lsb first a frame starts with the least or most significant data bit. then the next data bits, up to a total of eight, are succeed- ing, ending with the most or least significant bit accordingly. when a complete frame is transmitted, a new frame can directly follow it, or the communication line can be set to an idle (high) state. the udordn bit in ucsrnc sets the frame format used by the usart in mspim mode. the receiver and trans- mitter use the same setting. note that changing the setting of any of these bits will corrupt all ongoing communication for both the receiver and transmitter. 16-bit data transfer can be achieved by writing two data bytes to udr n. a uart transmit complete interrupt will then signal that the 16-bit value has been shifted out. table 21-2. ucpoln and ucphan functionality- ucpoln ucphan spi mode lead ing edge trailing edge 0 0 0 sample (rising) setup (falling) 0 1 1 setup (rising) sample (falling) 1 0 2 sample (falling) setup (rising) 1 1 3 setup (falling) sample (rising) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) ucpol=0 ucpol=1 ucpha=0 ucpha=1 201 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 21.5.1 usart mspim initialization the usart in mspim mode has to be initialized before any communication can take place. the initialization pro- cess normally consists of setting the baud rate, setting master mode of operation (by setting ddr_xckn to one), setting frame format and enabling the transmitter and the receiver. only the transmitter can operate indepen- dently. for interrupt driven usart operation, the global interrupt flag should be cleared (and thus interrupts globally disabled) when doing the initialization. note: to ensure immediate initialization of the xckn output th e baud-rate register (ubrrn) must be zero at the time the transmitter is enabled. contrary to the normal mode usar t operation the ubrrn must then be written to the desired value after the transmitter is enabled, but before the firs t transmission is started. setting ubrrn to zero before enabling the transmitter is not necessary if the initialization is done immediately after a reset since ubrrn is reset to zero. before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that there is no ongo- ing transmissions during the period the registers are c hanged. the txcn flag can be used to check that the transmitter has completed all transfers, and the rxcn flag can be used to check that there are no unread data in the receive buffer. note that the txcn flag must be cleared before each transmission (before udrn is written) if it is used for this purpose. the following simple usart initializat ion code examples show one assembly and one c function that are equal in functionality. the examples assume polling (no interrupts enabled). the baud rate is given as a function parame- ter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. 202 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. see ?about code examples? on page 7. assembly code example (1) usart_init: clr r18 out ubrrnh,r18 out ubrrnl,r18 ; setting the xckn port pin as output, enables master mode. sbi xckn_ddr, xckn ; set mspi mode of operation and spi data mode 0. ldi r18, (1< 204 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. see ?about code examples? on page 7. 21.6.1 transmitter and receiver flags and interrupts the rxcn, txcn, and udren flags and co rresponding interrupts in usart in mspim mode are i dentical in func- tion to the normal usart operation. however, the receiver error status flags (fe, dor, and pe) are not in use and is always read as zero. 21.6.2 disabling the transmitter or receiver the disabling of the transmitter or receiver in usart in mspim mode is identical in function to the normal usart operation. assembly code example (1) usart_mspim_transfer: ; wait for empty transmit buffer in r16, ucsrna sbrs r16, udren rjmp usart_mspim_transfer ; put data (r16) into buffer, sends the data out udrn,r16 ; wait for data to be received usart_mspim_wait_rxcn: in r16, ucsrna sbrs r16, rxcn rjmp usart_mspim_wait_rxcn ; get and return received data from buffer in r16, udrn ret c code example (1) unsigned char usart_receive( void ) { /* wait for empty transmit buffer */ while ( !( ucsrna & (1< 206 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 21.8 register description the following section describes the registers used for spi operation using the usart. 21.8.1 udrn ? usart mspi m i/o data register the function and bit description of th e usart data register (udrn) in mspi mode is identical to normal usart operation. see ?udrn ? usart i/o data register n? on page 194 . 21.8.2 ucsrna ? usart mspim control and status register n a ? bit 7 ? rxcn: usart receive complete this flag bit is set when there are unread data in the re ceive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disabled, the receive buffer will be flushed and conse- quently the rxcn bit will become zero. th e rxcn flag can be used to genera te a receive comple te interrupt (see description of the rxcien bit). ? bit 6 ? txcn: usart transmit complete this flag bit is set when the entire frame in the transmit shift register has been shifted out and there are no new data currently present in th e transmit buffer (udrn). the txcn flag bit is automatica lly cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. the txcn flag can generate a transmit complete interrupt (see description of the txcien bit). ? bit 5 ? udren: usart data register empty the udren flag indicates if the transmit buffer (udrn) is ready to receive new data. if udren is one, the buffer is empty, and therefore ready to be written. the udren flag can generate a data register empty interrupt (see description of the udrie bit). udren is set after a reset to indicate that the transmitter is ready. ? bit 4:0 ? reserved bits in mspi mode when in mspi mode, these bits are reserved for future us e. for compatibility with future devices, these bits must be written to zero when ucsrna is written. 21.8.3 ucsrnb ? usart mspim control and status register n b ? bit 7 ? rxcien: rx complete interrupt enable writing this bit to one enables inte rrupt on the rxcn flag. a usart rece ive complete interrupt will be generated only if the rxcien bit is written to one, the global interrupt flag in sreg is written to one and the rxcn bit in ucsrna is set. ? bit 6 ? txcien: tx complete interrupt enable writing this bit to one enab les interrupt on the txcn flag. a usart tr ansmit complete inte rrupt will be generated only if the txcien bit is written to one, the global interrup t flag in sreg is written to one and the txcn bit in ucs- rna is set. bit 7 6 5 4 3 2 1 0 rxcn txcn udren ? ? ? ? ? ucsrna read/write r r/w r r r r r r initial value 0 0 0 0 0 1 1 0 bit 7 6543210 rxcien txcien udrie rxenn txenn ? - - ucsrnb read/write r/w r/w r/w r/w r/w r r r initial value 0 0 0 0 0 1 1 0 207 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bit 5 ? udrie: usart data re gister empty interrupt enable writing this bit to one enables interr upt on the udren flag. a data regist er empty interrupt will be generated only if the udrie bit is written to one, the global interrupt flag in sreg is writ ten to one an d the udren bit in ucsrna is set. ? bit 4 ? rxenn: receiver enable writing this bit to one enables the usart receiver in mspim mode. the re ceiver will override normal port opera- tion for the rxdn pin when enabled. dis abling the receiver will flush the receiv e buffer. only enabling the receiver in mspi mode (i.e. setting rxenn=1 and txenn=0) has no meaning since it is the transmitter that controls the transfer clock and since only master mode is supported. ? bit 3 ? txenn: transmitter enable writing this bit to one enabl es the usart transmitter. t he transmitter will override no rmal port operation for the txdn pin when enabled. the disabling of the transmitter (writing txenn to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the transmit shift register and transmit buffer reg- ister do not contain data to be transm itted. when disabled, the tr ansmitter will no longer override the txdn port. ? bit 2:0 ? reserved bits in mspi mode when in mspi mode, these bits are reserved for future us e. for compatibility with future devices, these bits must be written to zero when ucsrnb is written. 21.8.4 ucsrnc ? usart mspim control and status register n c ? bit 7:6 ? umseln1:0: usart mode select these bits select the mode of oper ation of the usart as shown in table 21-4 . see ?ucsrnc ? usart control and status register n c? on page 196 for full description of the normal us art operation. the mspim is enabled when both umseln bits are set to one. the udordn, ucphan, and ucpoln can be set in the same write oper- ation where the mspim is enabled. ? bit 5:3 ? reserved bits in mspi mode when in mspi mode, these bits are reserved for future us e. for compatibility with future devices, these bits must be written to zero when ucsrnc is written. ? bit 2 ? udordn: data order when set to one the lsb of the data word is transmitted first. when set to zero the msb of the data word is trans- mitted first. refer to the frame formats section page 4 for details. bit 7 6 5 4 3 2 1 0 umseln1 umseln0 ? ? ? udordn ucphan ucpoln ucsrnc read/write r/w r/w r r r r/w r/w r/w initial value 0 0 0 0 0 1 1 0 table 21-4. umseln bits settings umseln1 umseln0 mode 0 0 asynchronous usart 0 1 synchronous usart 1 0 reserved 1 1 master spi (mspim) 208 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bit 1 ? ucphan: clock phase the ucphan bit setting determine if data is sampled on the leasing edge (first) or tailing (last) edge of xckn. refer to the spi data modes and timing section page 4 for details. ? bit 0 ? ucpoln: clock polarity the ucpoln bit sets the polarity of the xckn clock. the combination of the ucpoln and ucphan bit settings determine the timing of the data transfer. refer to the spi data modes and timing section page 4 for details. 21.8.5 usart mspim baud rate registers ? ubrrnl and ubrrnh the function and bit description of the baud rate registers in mspi mode is identical to normal usart operation. see ?ubrrnl and ubrrnh ? usart baud rate registers? on page 198. 209 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 22. 2-wire serial interface 22.1 features ? simple yet powerful and flexible communication interface, only two bus lines needed ? both master and sla ve operation supported ? device can operate as transmitter or receiver ? 7-bit address space allows up to 128 different slave addresses ? multi-master arbitration support ? up to 400khz data transfer speed ? slew-rate limited output drivers ? noise suppression ci rcuitry rejects spikes on bus lines ? fully programmable slave address with general call support ? address recognition causes wake-up when avr is in sleep mode ? compatible with philips? i 2 c protocol 22.2 2-wire serial in terface bus definition the 2-wire serial interface (twi) is ideally suited for ty pical microcontroller applicat ions. the twi protocol allows the systems designer to interco nnect up to 128 different devices using on ly two bi-directional bus lines, one for clock (scl) and one for data (sda). the only external hard ware needed to implement the bus is a single pull-up resistor for each of the twi bus lines. all devices connected to the bus have individual addresses, and mecha- nisms for resolving bus contention are inherent in the twi protocol. figure 22-1. twi bus interconnection device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc 210 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 22.2.1 twi terminology the following definitions are frequently encountered in this section. the prtwi bit in ?minimizing power cons umption? on page 41 must be written to zero to enable the 2-wire serial interface. 22.2.2 electrical interconnection as depicted in figure 22-1 , both bus lines are connected to the positive supply voltage through pull-up resistors. the bus drivers of all twi-compliant devices are open-drain or open-collector. this implements a wired-and func- tion which is essential to the operation of the interface. a low level on a twi bus line is generated when one or more twi devices output a zero. a high level is output when all twi devices tri-state their outputs, allowing the pull-up resistors to pull the line high. note that all avr devices connected to the twi bus must be powered in order to allow any bus operation. the number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400 pf and the 7-bit slave address space. a detailed specification of the electrical characteristics of the twi is given in ?two- wire serial interface characteristics? on page 315 . two different sets of specifications are presented there, one rel- evant for bus speeds below 100khz, and one valid for bus speeds up to 400khz. 22.3 data transfer and frame format 22.3.1 transferring bits each data bit transferred on the twi bus is accompanied by a pulse on the clock line. the level of the data line must be stable when the clock line is high. the only exception to this rule is for generating start and stop conditions. figure 22-2. data validity table 22-1. twi terminology term description master the device that initiates and terminates a transmission. the master also generates the scl clock. slave the device addressed by a master. transmitter the device placing data on the bus. receiver the device reading data from the bus. sda scl data stable data stable data change 211 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 22.3.2 start and stop conditions the master initiates and terminates a data transmission. t he transmission is initiated when the master issues a start condition on the bus, and it is terminated when the master issues a stop condition. between a start and a stop condition, the bus is considered busy, and no other master should try to seize control of the bus. a special case occurs when a new start condition is issued between a start and stop condition. this is referred to as a repeated start condit ion, and is used when the master wishes to init iate a new transfer with- out relinquishing control of the bus. after a repeated start, the bus is considered busy until the next stop. this is identical to the start behavior, and therefore start is used to describe both start and repeated start for the remainder of this datasheet, unless otherwise noted. as depicted below, start and stop condi- tions are signalled by changing the level of the sda line when the scl line is high. figure 22-3. start, repeated start and stop conditions 22.3.3 address packet format all address packets transmitted on the twi bus are 9 bits long, consisting of 7 add ress bits, one read/write control bit and an acknowledge bit. if the read/write bit is set, a read operation is to be performed, otherwise a write operation should be performed. when a slave recogni zes that it is being addressed, it should acknowledge by pulling sda low in the ninth scl (ack) cycle. if the addr essed slave is busy, or for some other reason can not service the master?s request, the sda line should be left high in the ack clock cycle. the master can then transmit a stop condition, or a repeated start condition to initiate a new transmi ssion. an address packet consisting of a slave address and a read or a write bi t is called sla+r or sla+w, respectively. the msb of the address byte is transmitted first. slave a ddresses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call. when a general call is issued, all sl aves should respond by pulling the sda line low in the ack cycle. a general call is used when a master wishes to transmit the same message to several slaves in the system. when the gen- eral call address followed by a write bit is transmitted on the bus, all slaves set up to acknowledge the general call will pull the sda line low in the ack c ycle. the following data packets will then be received by all the slaves that acknowledged the general call. note that transmitting the general call address followed by a read bit is meaning- less, as this would cause contention if several slaves started transmitting different data. all addresses of the format 1111 xxx should be reserved for future purposes. sda scl start stop repeated start stop start 212 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 22-4. address packet format 22.3.4 data packet format all data packets transmitted on the twi bus are nine bits long, consisting of one data byte and an acknowledge bit. during a data transfer, the master generates the clock and the start and stop conditions, while the receiver is responsible for acknowledging the rece ption. an acknowledge (ack) is sign alled by the receiver pulling the sda line low during the ninth scl cycle. if the receiver l eaves the sda line high, a nack is signalled. when the receiver has received the last byte, or for some reason c annot receive any more bytes, it should inform the trans- mitter by sending a nack after the final byte. the msb of the data byte is transmitted first. figure 22-5. data packet format 22.3.5 combining address and data packets into a transmission a transmission basically consists of a start condition, a sla+r/w, one or more data packets and a stop con- dition. an empty message, consisting of a start followed by a stop condition, is illegal. note that the wired- anding of the scl line can be used to implement hands haking between the master and the slave. the slave can extend the scl low period by pulling the scl line low. this is useful if the cl ock speed set up by the master is too fast for the slave, or the slave needs extra time for proc essing between the data transmissions. the slave extend- ing the scl low period will not a ffect the scl high period, which is dete rmined by the master . as a consequence, the slave can reduce the twi data transfer speed by prolonging the scl duty cycle. figure 22-6 shows a typical data transmissi on. note that several data bytes can be transmitted between the sla+r/w and the stop condition, depending on the software protocol implemented by the application software. sda scl start 12 789 addr msb addr lsb r/w ack 12 789 data msb data lsb ack aggregate sda sda from transmitter sda from receiver scl from master sla+r/w data byte stop, repeated start or next data byte 213 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 22-6. typical data transmission 22.4 multi-master bus systems, arbitration and synchronization the twi protocol allows bus systems with several master s. special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. two problems arise in multi-master systems: ? an algorithm must be implemented allowing only one of the masters to complete the transmission. all other masters should cease transmission when they discover that they have lost the selection process. this selection process is called arbitration. when a contending master discov ers that it has lost the arbitration process, it should immediately switch to slave mode to check whether it is being addressed by the winning master. the fact that multiple masters have started transmission at the same time should not be detectable to the slaves, i.e. the data being transferred on the bus must not be corrupted. ? different masters may use different scl frequencies. a scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. this will fac ilitate the arbitration process. the wired-anding of the bus lines is used to solve both these problems. the serial cl ocks from all masters will be wired-anded, yielding a combined clock with a high period equal to the one from the master with the shortest high period. the low period of the combined clock is equal to the low period of the master with the longest low period. note that all masters listen to the scl line, effectivel y starting to count their scl high and low time-out periods when the combined scl line goes high or low, respectively. 12 789 data byte data msb data lsb ack sda scl start 12 789 addr msb addr lsb r/w ack sla+r/w stop 214 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 22-7. scl synchronization betw een multiple masters arbitration is carried out by all masters continuously monitoring the sda line after outputting data. if the value read from the sda line does not match the value the master had output, it has lost the arbitration. note that a master can only lose arbitration when it outputs a high sda val ue while another master outputs a low value. the losing master should immediately go to slave mode, checking if it is being addressed by the winning master. the sda line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or address packet. arbitration will conti nue until only one master remains, and this may take many bits. if several masters are trying to address the same slave, arbitration will continue into the data packet. figure 22-8. arbitration between two masters note that arbitration is not allowed between: ? a repeated start condition and a data bit. ? a stop condition and a data bit. ta low ta high scl from master a scl from master b scl bus line tb low tb high masters start counting low period masters start counting high period sda from master a sda from master b sda line synchronized scl line start master a loses arbitration, sda a sda 215 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? a repeated start and a stop condition. it is the user software?s responsibility to ensure that thes e illegal arbitration conditions never occur. this implies that in multi-master systems, all data transfers must use the same composition of sla+r/w and data packets. in other words: all transmissions must contain the same num ber of data packets, otherwise the result of the arbitra- tion is undefined. 22.5 overview of the twi module the twi module is comprised of several submodules, as shown in figure 22-9 . all registers drawn in a thick line are accessible through the avr data bus. figure 22-9. overview of the twi module 22.5.1 scl and sda pins these pins interface the avr twi with the rest of the m cu system. the output drivers contain a slew-rate limiter in order to conform to the twi specification. the input stages contain a spike suppre ssion unit removing spikes shorter than 50 ns. note that the internal pull-ups in the avr pads can be enabled by setting the port bits corre- sponding to the scl and sda pins, as explained in the i/o port section. the internal pull-ups can in some systems eliminate the need for external ones. 22.5.2 bit rate generator unit this unit controls the period of scl when operating in a master mode. the scl period is controlled by settings in the twi bit rate register (twbr) and the prescaler bi ts in the twi status regi ster (twsr). slave operation does not depend on bit rate or prescaler settings, but the cpu clock frequency in the slave must be at least 16 twi unit address register (twar) address match unit address comparator control unit control register (twcr) status register (twsr) state machine and status control scl slew-rate control spike filter sda slew-rate control spike filter bit rate generator bit rate register (twbr) prescaler bus interface unit start / stop control arbitration detection ack spike suppression address/data shift register (twdr) 216 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 times higher than the scl frequency. note that slaves may prolong the scl low period, thereby reducing the aver- age twi bus clock period. the scl frequency is generated according to the following equation: ? twbr = value of the twi bit rate register. ? prescalervalue = value of the prescaler, see table 22-7 on page 236 . note: pull-up resistor values should be selected according to the scl frequency and the capacitive bus line load. see table 29-19 on page 315 for value of pull-up resistor. 22.5.3 bus interface unit this unit contains the data and address shift register (twdr), a start/stop controller and arbitration detec- tion hardware. the twdr contains the address or data bytes to be transmitted, or the address or data bytes received. in addition to the 8-bit twdr, the bus interface un it also contains a register containing the (n)ack bit to be transmitted or received. this (n)ack register is not directly accessible by the application software. however, when receiving, it can be set or cleared by manipulating the twi control register (twcr). when in transmitter mode, the value of the received (n)ack bit can be determined by the value in the twsr. the start/stop controller is responsible for generation and detection of start, repeated start, and stop conditions. the start/stop controller is able to detect start and stop conditions even when the avr mcu is in one of the sleep modes, enabling the mcu to wake up if addressed by a master. if the twi has initiated a transmission as master, the ar bitration detection hardware continuously monitors the transmission trying to determine if arbitration is in proces s. if the twi has lost an arbitration, the control unit is informed. correct action can then be taken and appropriate status codes generated. 22.5.4 address match unit the address match unit checks if received address byte s match the seven-bit address in the twi address regis- ter (twar). if the twi general call recognition enable (t wgce) bit in the twar is written to one, all incoming address bits will also be compared ag ainst the general call address. upon an address match, the control unit is informed, allowing correct action to be taken. the twi may or may not acknowledge its address, depending on set- tings in the twcr. the address match unit is able to compare addresses even when the avr mcu is in sleep mode, enabling the mcu to wake up if addressed by a master. 22.5.5 control unit the control unit monitors the twi bus and generates respon ses corresponding to settings in the twi control reg- ister (twcr). when an event requiring the attention of the application occurs on the twi bus, the twi interrupt flag (twint) is asserted. in the next clock cycle, the tw i status register (twsr) is updated with a status code identifying the event. the twsr only contains relevant status information when the twi interrupt flag is asserted. at all other times, the twsr contains a special status c ode indicating that no relevant status information is avail- able. as long as the twint flag is set, the scl line is held low. this allows the application softwar e to complete its tasks before allowing the twi transmission to continue. the twint flag is set in the following situations: ? after the twi has transmitted a start/repeated start condition. ? after the twi has transmitted sla+r/w. ? after the twi has transmitted an address byte. ? after the twi has lost arbitration. ? after the twi has been addressed by own slave address or general call. ? after the twi has received a data byte. scl frequency cpu clock frequency 16 2 (twbr) prescalervalue ?? ? + ---------------------------------------------------------------------------------------- - = 217 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? after a stop or repeated start has been received while still ad dressed as a slave. ? when a bus error has occurred due to an illegal start or stop condition. 22.6 using the twi the avr twi is byte-oriented and interrupt based. interrupts are issued after all bus events, like reception of a byte or transmission of a start condition. because the twi is interrupt-based, the application software is free to carry on other operations during a twi byte transfer. note that the twi interrupt enable (twie) bit in twcr together with the global interrupt enable bit in sreg allow the application to decide whether or not assertion of the twint flag should generate an interrupt request. if the twie bit is cleared, the application must poll the twint flag in order to detect actions on the twi bus. when the twint flag is asserted, t he twi has finished an operation and awaits application response. in this case, the twi status register (twsr) contains a value in dicating the current state of the twi bus. the application software can then decide how the twi should behave in the next twi bu s cycle by manipulating the twcr and twdr registers. figure 22-10 is a simple example of how the application can inte rface to the twi hardware. in this example, a mas- ter wishes to transmit a single data byte to a slave. this description is quite abstract, a more detailed explanation follows later in this section. a simple code example implementing the desired behavior is also presented. figure 22-10. interfacing the application to the twi in a typical transmission 1. the first step in a twi transmission is to transmit a star t condition. this is done by writing a specific value into twcr, instructing the twi hardware to transmit a start condition. which value to write is described later on. however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the twin t bit in twcr is set. immediately after the application has cleared twint, the twi will initiate trans mission of the start condition. 2. when the start condition has been transmitted, the twint flag in twcr is set, and twsr is updated with a status code indicating that the start condition has successfully been sent. 3. the application software should now examine the value of twsr, to make sure that the start condition was successfully transmitted. if twsr indicates otherwise, the application software might take some spe- cial action, like calling an error routin e. assuming that the status code is as expected, the application must load sla+w into twdr. remember that twdr is used both for address and data. after twdr has been loaded with the desired sla+w, a specific value must be written to twcr, instructing the twi hardware to transmit the sla+w present in twdr. which value to write is described later on. however, it is important start sla+w a data a stop 1. application writes to twcr to initiate transmission of start 2. twint set. status code indicates start condition sent 4. twint set. status code indicates sla+w sent, ack received 6. twint set. status code indicates data sent, ack received 3. check twsr to see if start was sent. application loads sla+w into twdr, and loads appropriate control signals into twcr, makin sure that twint is written to one, and twsta is written to zero. 5. check twsr to see if sla+w was sent and ack received. application loads data into twdr, and loads appropriate control signals into twcr, making sure that twint is written to one 7. check twsr to see if data was sent and ack received. application loads appropriate control signals to send stop into twcr, making sure that twint is written to one twi bus indicates twint set application action twi hardware action 218 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 that the twint bit is set in the value written. writin g a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. immediately after the application has cleared twint, the twi will initiate tran smission of the address packet. 4. when the address packet has been transmitted, the twint flag in twcr is set, and twsr is updated with a status code indicati ng that the address packet has successfully been sent. the status code will also reflect whether a slave acknowledged the packet or not. 5. the application software should now examine the value of twsr, to make sure that the address packet was successfully transmitted, and that the value of the ack bit was as expected. if twsr indicates other- wise, the application software might take some special action, like calling an error routine. assuming that the status code is as expected, the application must load a data packet into twdr. subsequently, a spe- cific value must be written to twcr, instructing the twi hardware to transmit the data packet present in twdr. which value to write is described later on. howeve r, it is important that the twint bit is set in the value written. writing a one to twint clears the flag . the twi will not start any ope ration as long as the twint bit in twcr is set. immediately after the application has cleared twint, the twi will initiate trans- mission of the data packet. 6. when the data packet has been transmitted, the twint flag in twcr is set, and twsr is updated with a status code indicating that the data packet has successfully been sent . the status code will also reflect whether a slave acknowledged the packet or not. 7. the application software should now examine the value of twsr, to make sure that the data packet was successfully transmitted, and that the value of the ack bit was as expected. if twsr indicates otherwise, the application software might take some special action, like calling an error routine. assu ming that the sta- tus code is as expected, the applic ation must write a specific value to twcr, instructing the twi hardware to transmit a stop condition. which value to write is described later on. however, it is important that the twint bit is set in the value writte n. writing a one to twint clears th e flag. the twi will not start any oper- ation as long as the twint bit in twcr is set. immediately after the application has cleared twint, the twi will initiate transmission of the stop condition. note that twint is not set after a stop condition has been sent. even though this example is simple, it shows the principl es involved in all twi transmissions. these can be sum- marized as follows: ? when the twi has finished an operation and expects application response, the twint flag is set. the scl line is pulled low until twint is cleared. ? when the twint flag is set, the user must update all twi registers with the value relevant for the next twi bus cycle. as an example, twdr must be loaded with the value to be transmitted in the next bus cycle. ? after all twi register updates and other pending application software tasks have been completed, twcr is written. when writing twcr, the twin t bit should be set. writing a one to twint clears the flag. the twi will then commence executing whatever operation was specified by the twcr setting. in the following an assembly and c implementation of the example is given. note that the code below assumes that several definitions have been made, for example by using include-files. 219 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 table 2. assembly code example c example comments 1 ldi r16, (1< 221 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 a start condition is sent by wr iting the following value to twcr: twen must be set to enable the 2-wire serial interface, twsta must be written to one to transmit a start con- dition and twint must be wr itten to one to clear the twint flag. the twi will then test the 2-wire serial bus and generate a start condition as soon as the bus becomes free. after a start condition has been transmitted, the twint flag is set by hardware, and the status code in twsr will be 0x08 (see table 22-2 ). in order to enter mt mode, sla+w must be transmitted. this is done by writ ing sla+w to twdr. thereafter the twint bit should be cleared (by writing it to one) to cont inue the transfer. this is accomplished by writing the follo wing value to twcr: when sla+w have been transmitted and an acknowledgement bit has been received, twint is set again and a number of status codes in twsr are possible. possible st atus codes in master mode are 0x18, 0x20, or 0x38. the appropriate action to be taken for each of these status codes is detailed in table 22-2 . when sla+w has been successfully transmitted, a data packet should be transmitted. this is done by writing the data byte to twdr. twdr must only be written when tw int is high. if not, the acce ss will be discarded, and the write collision bit (twwc) will be set in the twcr re gister. after updating twdr, the twint bit should be cleared (by writing it to one) to cont inue the transfer. this is accomplished by writing the follo wing value to twcr: this scheme is repeated until the last byte has been sent and the transfer is ended by generating a stop condi- tion or a repeated start condition. a stop condition is generated by writing the following value to twcr: a repeated start condition is generated by writing th e following value to twcr: after a repeated start condition (state 0x10) the 2-wire se rial interface can access the same slave again, or a new slave without transmitting a stop condition. repeat ed start enables the master to switch between slaves, master transmitter mode and master receiver mode without losing control of the bus. twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x 222 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 table 22-2. status codes for master transmitter mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twin t twe a 0x08 a start condition has been transmitted load sla+w 0 0 1 x sla+w will be transmitted; ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+w or load sla+r 0 0 0 0 1 1 x x sla+w will be transmitted; ack or not ack will be received sla+r will be transmitted; logic will switch to master receiver mode 0x18 sla+w has been transmitted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x20 sla+w has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x28 data byte has been transmit- ted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x30 data byte has been transmit- ted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x38 arbitration lost in sla+w or data bytes no twdr action or no twdr action 0 1 0 0 1 1 x x 2-wire serial bus will be released and not addressed slave mode entered a start condition will be transmitted when the bus becomes free 223 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 22-12. formats and states in the master transmitter mode 22.7.2 master receiver mode in the master receiver mode, a number of data bytes are received from a slave transmitter (slave see figure 22- 13 ). in order to enter a master mode, a start condition must be transmitted. the format of the following address packet determines whether master transmitter or master receiver mode is to be entered. if sla+w is transmitted, mt mode is entered, if sla+r is transmitted, mr mode is entered. all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. s sla w a data a p $08 $18 $28 r sla w $10 ap $20 p $30 a or a $38 a other master continues a or a $38 other master continues r a $68 other master continues $78 $b0 to corresponding states in slave mode mt m r successfull transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the 2-wire serial bus. the p rescaler bits are zero or masked to zero s 224 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 22-13. data transfer in ma ster receiver mode a start condition is sent by wr iting the following value to twcr: twen must be written to one to enable the 2-wire serial interface, twsta must be written to one to transmit a start condition and twint must be set to clear the twin t flag. the twi will then test the 2-wire serial bus and generate a start condition as soon as the bus becomes free. after a start condition has been transmitted, the twint flag is set by hardware, and the status code in twsr will be 0x08 (see table 22-2 ). in order to enter mr mode, sla+r must be transmitted. this is done by writ ing sla+r to twdr. thereafter the twint bit should be cleared (by writing it to one) to cont inue the transfer. this is accomplished by writing the follo wing value to twcr: when sla+r have been transmitted and an acknowledgement bit has been received, twint is set again and a number of status codes in twsr are possible. possible st atus codes in master mode are 0x38, 0x40, or 0x48. the appropriate action to be taken for each of these status codes is detailed in table 22-3 . received data can be read from the twdr register when the twint flag is set high by hardware. this scheme is repeated until the last byte has been received. after the last byte has been received, the mr should inform the st by sending a nack after the last received data byte. the transfer is ended by generating a stop condition or a repeated start condition. a stop condition is generated by writing the following value to twcr: a repeated start condition is generated by writing th e following value to twcr: after a repeated start condition (state 0x10) the 2-wire se rial interface can access the same slave again, or a new slave without transmitting a stop condition. repeat ed start enables the master to switch between slaves, master transmitter mode and master receiver mode without losing control over the bus. twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x device 1 master receiver device 2 slave transmitter device 3 device n sda scl ........ r1 r2 v cc 225 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 table 22-3. status codes for master receiver mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twin t twe a 0x08 a start condition has been transmitted load sla+r 0 0 1 x sla+r will be transmitted ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+r or load sla+w 0 0 0 0 1 1 x x sla+r will be transmitted ack or not ack will be received sla+w will be transmitted logic will switch to master transmitter mode 0x38 arbitration lost in sla+r or not ack bit no twdr action or no twdr action 0 1 0 0 1 1 x x 2-wire serial bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free 0x40 sla+r has been transmitted; ack has been received no twdr action or no twdr action 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x48 sla+r has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x50 data byte has been received; ack has been returned read data byte or read data byte 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x58 data byte has been received; not ack has been returned read data byte or read data byte or read data byte 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 226 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 22-14. formats and states in the master receiver mode 22.7.3 slave receiver mode in the slave receiver mode, a number of data bytes are received from a master transmitter (see figure 22-15 ). all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. figure 22-15. data transfer in slave receiver mode to initiate the slave receiver mode, twar and twcr must be initialized as follows: s sla r a data a $08 $40 $50 sla r $10 ap $48 a or a $38 other master continues $38 other master continues w a $68 other master continues $78 $b0 to corresponding states in slave mode mr m t successfull reception from a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the 2-wire serial bus. the p rescaler bits are zero or masked to zero p data a $58 a r s twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address device 3 device n sda scl ........ r1 r2 v cc device 2 master transmitter device 1 slave receiver 227 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 the upper 7 bits are th e address to which the 2-wire serial interface will respond when addressed by a master. if the lsb is set, the twi will respond to the general call address (0x00), otherwise it will ignore the general call address. twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledge- ment of the device?s own slave address or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi waits until it is addressed by its own slave address (or the general call address if en abled) followed by the data dire ction bit. if the direction bit is ?0? (write), the twi will oper- ate in sr mode, otherwise st mode is entered. after its own slave address and the write bit have been received, the twint flag is set and a valid status code can be re ad from twsr. the status code is used to determine the appropriate software action. the appropriate action to be taken for each status code is detailed in table 22-4 . the slave receiver mode may also be entered if arbitration is lost while the twi is in the master mode (see states 0x68 and 0x78). if the twea bit is reset during a transfer, the twi will return a ?not acknowledge? (?1?) to sda after the next received data byte. this can be used to indicate that the slave is not able to receive any more bytes. while twea is zero, the twi does not acknowledge its own slave addre ss. however, the 2-wire seri al bus is still monitored and address recognition may resume at any time by setting twea. this implies that the twea bit may be used to tem- porarily isolate the twi from the 2-wire serial bus. in all sleep modes other than idle mode , the clock system to the twi is turned off. if the twea bit is set, the inter- face can still acknowledge its own slave address or the ge neral call address by using the 2-wire serial bus clock as a clock source. the part will then wake up from sleep and the twi will ho ld the scl clock low during the wake up and until the twint flag is cleared (by writing it to one). furthe r data reception will be ca rried out as normal, with the avr clocks running as normal. observe that if the avr is set up with a long start-up time, the scl line may be held low for a long time, blocking other data transmissions. note that the 2-wire serial interface data register ? tw dr does not reflect the last byte present on the bus when waking up from these sleep modes. twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x 228 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 table 22-4. status codes for slave receiver mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hard- ware application software response next action taken by twi hardware to/from twdr to twcr sta sto twin t twe a 0x60 own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x68 arbitration lost in sla+r/w as master; own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x70 general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x78 arbitration lost in sla+r/w as master; general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x80 previously addressed with own sla+w; data has been received; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x88 previously addressed with own sla+w; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0x90 previously addressed with general call; data has been re- ceived; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x98 previously addressed with general call; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xa0 a stop condition or repeated start condition has been received while still addressed as slave no action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 229 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 22-16. formats and states in the slave receiver mode 22.7.4 slave transmitter mode in the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see figure 22-17 ). all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. figure 22-17. data transfer in slave transmitter mode s sla w a data a $60 $80 $88 a $68 reception of the own slave address and one or more data bytes. all are acknowledged last data byte received is not acknowledged arbitration lost as master and addressed as slave reception of the general call address and one or more data bytes last data byte received is not acknowledged n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the 2-wire serial bus. the prescaler bits are zero or masked to zero p or s data a $80 $a0 p or s a adataa $70 $90 $98 a $78 p or s data a $90 $a0 p or s a general call arbitration lost as master and addressed as slave by general call data a device 3 device n sda scl ........ r1 r2 v cc device 2 master receiver device 1 slave transmitter 230 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 to initiate the slave transmitter mode, twar and twcr must be initialized as follows: the upper seven bits ar e the address to which the 2-wire serial in terface will respond when addressed by a mas- ter. if the lsb is set, the twi will resp ond to the gene ral call address (0x00) , otherwise it will ignore the general call address. twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledge- ment of the device?s own slave address or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi waits until it is addressed by its own slave address (or the general call address if enabled) followed by th e data direction bit. if the direction bit is ?1? (read), the twi will oper- ate in st mode, otherwise sr mode is entered. after it s own slave address and the write bit have been received, the twint flag is set and a valid status code can be re ad from twsr. the status code is used to determine the appropriate software action. the appropriate action to be taken for each status code is detailed in table 22-5 . the slave transmitter mode may also be entered if arbitration is lost while the twi is in the master mode (see state 0xb0). if the twea bit is written to zero durin g a transfer, the twi will transmit the last byte of the tran sfer. state 0xc0 or state 0xc8 will be entered, depending on whether the mast er receiver transmits a nack or ack after the final byte. the twi is switched to the not ad dressed slave mode, and will ignore the master if it continues the transfer. thus the master receiver receives all ?1? as serial data. state 0xc8 is entered if the master demands additional data bytes (by transmitting ack), even though the slave ha s transmitted the last byte (twea zero and expecting nack from the master). while twea is zero, the twi does not respond to its own sl ave address. however, the 2-wire serial bus is still monitored and address recognition may resume at any time by setting twea. this implies that the twea bit may be used to temporarily isolate the twi from the 2-wire serial bus. in all sleep modes other than idle mode , the clock system to the twi is turned off. if the twea bit is set, the inter- face can still acknowledge its own slave address or the ge neral call address by using the 2-wire serial bus clock as a clock source. the part will t hen wake up from sleep and the twi will hold the scl clock will low during the wake up and until the twint flag is cleared (by writing it to one). fu rther data transmission will be carried out as normal, with the avr clocks running as normal. observe that if t he avr is set up with a long start-up time, the scl line may be held low for a long time, blocking other data transmissions. note that the 2-wire serial interface data register ? tw dr does not reflect the last byte present on the bus when waking up from these sleep modes. twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x 231 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 table 22-5. status codes for slave transmitter mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hard- ware application software response next action taken by twi hardware to/from twdr to twcr sta sto twin t twe a 0xa8 own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xb0 arbitration lost in sla+r/w as master; own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xb8 data byte in twdr has been transmitted; ack has been received load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xc0 data byte in twdr has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xc8 last data byte in twdr has been transmitted (twea = ?0?); ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 232 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 22-18. formats and states in the slave transmitter mode 22.7.5 miscellaneous states there are two status codes that do not correspond to a defined twi state, see table 22-6 . status 0xf8 indicates that no relevant information is available because the twint flag is not set. this occurs between other states, and when the twi is not involved in a serial transfer. status 0x00 indicates that a bus error has occurred during a 2-wire serial bus transfer. a bus error occurs when a start or stop condition occurs at an illegal position in the format frame. examples of such illegal positions are during the serial transfer of an address byte, a data by te, or an acknowledge bit. when a bus error occurs, twint is set. to recover from a bus error, the twsto flag must set and twint must be cleared by writing a logic one to it. this causes the twi to enter the not addressed slave mode and to clear the twsto flag (no other bits in twcr are affected). the sda and scl lines are released, and no stop condition is transmitted. 22.7.6 combining several twi modes in some cases, several twi modes must be combined in order to complete the desired action. consider for exam- ple reading data from a serial eeprom. typically , such a transfer involves the following steps: 1. the transfer must be initiated. 2. the eeprom must be instructed what location should be read. 3. the reading must be performed. 4. the transfer must be finished. note that data is transmitted both from master to slave and vice versa. the master must instruct the slave what location it wants to read, requiring the use of the mt mode. subsequently, data must be read from the slave, imply- ing the use of the mr mode. thus, the transfer direction must be changed. the master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation. if this principle is violated s sla r a data a $a8 $b8 a $b0 reception of the own slave address and one or more data bytes last data byte transmitted. switched to not addressed slave (twea = '0') arbitration lost as master and addressed as slave n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the 2-wire serial bus. the prescaler bits are zero or masked to zero p or s data $c0 data a a $c8 p or s all 1's a table 22-6. miscellaneous states status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twin t twe a 0xf8 no relevant state information available; twint = ?0? no twdr action no twcr action wait or proceed current transfer 0x00 bus error due to an illegal start or stop condition no twdr action 0 1 1 x only the internal hardware is affected, no stop condi- tion is sent on the bus. in all cases, the bus is released and twsto is cleared. 233 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 in a multi master system, another mast er can alter the data pointer in the eeprom between steps 2 and 3, and the master will read the wrong data location. such a change in transfer di rection is accomplished by transmitting a repeated start between the transmission of the address byte and reception of the data. after a repeated start, the master keeps ownership of the bus. the following figure shows the flow in this transfer. figure 22-19. combining several twi modes to access a serial eeprom 22.8 multi-master syst ems and arbitration if multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one or more of them. the twi standard ensu res that such situations ar e handled in such a way that one of the masters will be allowed to proceed with the tran sfer, and that no data will be lost in the pr ocess. an example of an arbitration situ- ation is depicted below, where two masters are trying to transmit data to a slave receiver. figure 22-20. an arbitration example several different scenarios may arise during arbitration, as described below: ? two or more masters are performing identical communication with the same slave. in this case, neither the slave nor any of the masters will know about the bus contention. ? two or more masters are acce ssing the same slave with different data or direction bit. in this case, arbitration will occur, either in the read/write bit or in the data bits. the masters trying to output a one on sda while another master outputs a zero will lose the arbi tration. losing masters w ill switch to not addressed slave mode or wait until the bus is free and transmit a new start cond ition, depending on application software action. ? two or more masters are accessing di fferent slaves. in this case, arbitrat ion will occur in the sla bits. masters trying to output a one on sda while another mast er outputs a zero will lose the arbitration. masters losing arbitration in sla will switch to slave mode to check if they are being addressed by the winning master. if addressed, they will switch to sr or st mode, depending on the value of the read/write bit. if they are not being addressed, they will switch to no t addressed slave mode or wait until the bus is free and transmit a new start condition, depending on application software action. this is summarized in figure 22-21 . possible status values are given in circles. master transmitter master receiver s = start rs = repeated start p = stop transmitted from master to slave transmitted from slave to master s sla+w a address a rs sla+r a data a p device 1 master transmitter device 2 master transmitter device 3 slave receiver device n sda scl ........ r1 r2 v cc 234 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 22-21. possible status codes caused by arbitration own address / general call received arbitration lost in sla twi bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free no arbitration lost in data direction ye s write data byte will be received and not ack will be returned data byte will be received and ack will be returned last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received read b0 68/78 38 sla start data stop 235 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 22.9 register description 22.9.1 twbr ? twi bit rate register ? bits 7...0 ? twi bit rate register twbr selects the division factor for the bit rate generator. the bit rate generator is a frequency divider which gen- erates the scl clock frequency in the master modes. see ?bit rate generator unit? on page 215 for calculating bit rates. 22.9.2 twcr ? twi control register the twcr is used to control the operation of the twi. it is used to enable the twi, to initiate a master access by applying a start condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the twdr. it also indicates a write collision if data is attemp ted written to twdr while t he register is inaccessible. ? bit 7 ? twint: twi interrupt flag this bit is set by hardware when the twi has finished its current job and expects application software response. if the i-bit in sreg and twie in twcr are set, the mcu will jump to the twi interrupt vector. while the twint flag is set, the scl low period is stretched. the twint flag must be cleared by software by writing a logic one to it. note that this flag is not automatically cleared by hardware when executing the interrupt routine. also note that clearing this flag starts the operation of the twi, so a ll accesses to the twi address register (twar), twi status register (twsr), and twi data register (twdr) must be complete before clearing this flag. ? bit 6 ? twea: twi enable acknowledge bit the twea bit controls the generation of the acknowledge pulse. if the twea bit is written to one, the ack pulse is generated on the twi bus if the following conditions are met: 1. the device?s own slave address has been received. 2. a general call has been received, while the twgce bit in the twar is set. 3. a data byte has been received in master receiver or slave receiver mode. by writing the twea bit to zero, the device can be virtually disconnected from the 2-wire serial bus temporarily. address recognition can then be resumed by writing the twea bit to one again. ? bit 5 ? twsta: twi start condition bit the application writes the twsta bit to one when it desires to become a master on the 2-wire serial bus. the twi hardware checks if the bus is available, and generates a start condition on the bus if it is free. however, if the bus is not free, the twi waits until a stop condition is detected, and then generates a new start condition to claim the bus master status. twsta must be cleared by software when the start condition has been transmitted. bit 76543210 (0xb8) twbr7 twbr6 twbr5 twbr4 twbr3 twbr2 twbr1 twbr0 twbr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0xbc) twint twea twsta twsto twwc twen ? twie twcr read/write r/w r/w r/w r/w r r/w r r/w initial value 0 0 0 0 0 0 0 0 236 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bit 4 ? twsto: twi stop condition bit writing the twsto bit to one in mast er mode will generate a stop condition on the 2-wire serial bus. when the stop condition is executed on the bus, the twsto bit is cleared automatically. in slave mode, setting the twsto bit can be used to recover from an error conditi on. this will not generate a stop condition, but the twi returns to a well-defined unaddressed slave mode and releases the scl and sda lines to a high impedance state. ? bit 3 ? twwc: twi write collision flag the twwc bit is set when attempting to write to the twi data register ? twdr when twint is low. this flag is cleared by writing the twdr register when twint is high. ? bit 2 ? twen: twi enable bit the twen bit enables twi operation and activates the twi interface. when twen is written to one, the twi takes control over the i/o pins connected to the scl and sda pins, enabling the slew-rate limiters and spike filters. if this bit is written to zero, the twi is switched off and all twi transmissions are terminated, regardless of any ongoing operation. ? bit 1 ? reserved this bit is a reserved bit and will always read as zero. ? bit 0 ? twie: twi interrupt enable when this bit is written to one, and th e i-bit in sreg is set, t he twi interrupt request will be activated for as long as the twint flag is high. 22.9.3 twsr ? twi status register ? bits 7:3 ? tws: twi status these 5 bits reflect the status of the twi logic and the 2-wire serial bus. the different status codes are described later in this section. note that the value read from twsr contains both the 5-bit status value and the 2-bit prescaler value. the application designer should mask the prescaler bits to zero when checking the status bits. this makes status checking independent of prescaler setting. this app roach is used in this datasheet, unless otherwise noted. ? bit 2 ? reserved this bit is reserved and will always read as zero. ? bits 1:0 ? twps: twi prescaler bits these bits can be read and written, and control the bit rate prescaler. to calculate bit rates, see ?bit rate generator unit? on page 215 . the value of twps1...0 is used in the equation. bit 76543210 (0xb9) tws7 tws6 tws5 tws4 tws3 ? twps1 twps0 twsr read/write r r r r r r r/w r/w initial value11111000 table 22-7. twi bit rate prescaler twps1 twps0 prescaler value 001 014 1016 1164 237 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 22.9.4 twdr ? twi data register in transmit mode, twdr contains the next byte to be transmitted. in receive mode, the twdr contains the last byte received. it is writable while the tw i is not in the process of shifting a by te. this occurs when the twi interrupt flag (twint) is set by hardware. note that the data register cannot be initialized by the user before the first inter- rupt occurs. the data in twdr remains stable as long as twint is set. while data is shifted out, data on the bus is simultaneously shifte d in. twdr always contains the last byte present on the bus, except after a wake up from a sleep mode by the twi interrupt. in this case, the contents of twdr is undefined. in the case of a lost bus arbitra- tion, no data is lost in the transition from master to slave. handling of the ack bit is controlled automatically by the twi logic, the cpu cannot access the ack bit directly. ? bits 7:0 ? twd: twi data register these eight bits constitute the next data byte to be transmi tted, or the latest data byte received on the 2-wire serial bus. 22.9.5 twar ? twi (slave) address register the twar should be loaded with the 7-bit slave address (i n the seven most significant bits of twar) to which the twi will respond when programmed as a slave transmitter or receiver, and not needed in t he master modes. in multi master systems, twar must be set in masters which can be addressed as slaves by other masters. the lsb of twar is used to enable recognition of the general call address (0x00). there is an associated address comparator that looks for the slave address (or general ca ll address if enabled) in the received serial address. if a match is found, an interrupt request is generated. ? bits 7:1 ? twa: twi (slave) address register these seven bits constitute the slave address of the twi unit. ? bit 0 ? twgce: twi general call recognition enable bit if set, this bit enables the recognition of a general call given over the 2-wire serial bus. 22.9.6 twamr ? twi (slave) address mask register ? bits 7:1 ? twam: twi address mask the twamr can be loaded with a 7-bit salve address mask. ea ch of the bits in twamr can mask (disable) the corresponding address bits in the twi address register (twar). if the mask bit is set to one then the address match logic ignores the compare between the incoming address bit and the corresponding bit in twar. figure 22- 22 shown the address match logic in detail. bit 76543210 (0xbb) twd7 twd6 twd5 twd4 twd3 twd2 twd1 twd0 twdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 bit 76543210 (0xba) twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce twar read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111110 bit 76543210 (0xbd) twam[6:0] ? twamr read/write r/w r/w r/w r/w r/w r/w r/w r initial value 0 0 0 0 0 0 0 0 238 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 22-22. twi address match logic, block diagram ? bit 0 ? reserved this bit is an unused bit in t he atmega48a/pa/88a/pa/1 68a/pa/328/p, and will always read as zero. address match address bit comparator 0 address bit comparator 6..1 twar0 twamr0 address bit 0 239 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 23. analog comparator 23.1 overview the analog comparator compares the input values on the positive pin ain0 and negative pin ain1. when the volt- age on the positive pin ain0 is higher than the voltage on the negative pin ain1, the analog comparator output, aco, is set. the comparator?s output can be set to trigger the timer/counter1 input capture function. in addition, the comparator can trigger a separate interrupt, exclusive to the analog comparator. the user can select interrupt triggering on comparator output rise, fall or toggle. a block diagram of the comparator and its surrounding logic is shown in figure 23-1 . the power reduction adc bit, pradc, in ?minimizing power cons umption? on page 41 must be disabled by writ- ing a logical zero to be able to use the adc input mux. figure 23-1. analog comparator block diagram (2) notes: 1. see table 23-1 on page 239 . 2. refer to figure 1-1 on page 2 and table 14-9 on page 89 for analog comparator pin placement. 23.2 analog comparator multiplexed input it is possible to select any of the adc7...0 pins to replace the negative input to the analog comparator. the adc multiplexer is used to select this inpu t, and consequently, the adc must be switched off to utilize this feature. if the analog comparator multiplexe r enable bit (acme in adcsrb) is set an d the adc is switched off (aden in adc- sra is zero), mux2...0 in admux select the input pin to replace the negative input to the analog comparator, as shown in table 23-1 . if acme is cleared or aden is set, ain1 is applied to the negative input to the analog comparator. acbg bandgap reference adc multiplexer output acme aden (1) table 23-1. analog comparator multiplexed input acme aden mux2...0 analog co mparator negative input 0 x xxx ain1 1 1 xxx ain1 1 0 000 adc0 1 0 001 adc1 1 0 010 adc2 1 0 011 adc3 240 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 23.3 register description 23.3.1 adcsrb ? adc control and status register b ? bit 6 ? acme: analog comparator multiplexer enable when this bit is written logic one and the adc is switch ed off (aden in adcsra is zero), the adc multiplexer selects the negative input to the analog comparator. when this bit is written logic zero, ain1 is applied to the neg- ative input of the analog comparator. for a detailed description of this bit, see ?analog comparator multiplexed input? on page 239 . 23.3.2 acsr ? analog comparator control and status register ? bit 7 ? acd: analog comparator disable when this bit is written logic one, the power to the analog comparator is switched off. this bit can be set at any time to turn off the analog comparator . this will reduce power consumption in active and idle mode. when chang- ing the acd bit, the analog comparator interrupt must be disabled by clearing the acie bit in acsr. otherwise an interrupt can occur when the bit is changed. ? bit 6 ? acbg: analog comparator bandgap select when this bit is set, a fixed bandgap reference voltage repl aces the positive input to the analog comparator. when this bit is cleared, ain0 is applied to the positive i nput of the analog comparator. when the bandgap reference is used as input to the analog comparator, it will take a cert ain time for the voltage to stabilize. if not stabilized, the first conversion may give a wrong value. see ?internal voltage reference? on page 49 ? bit 5 ? aco: analog comparator output the output of the analog comparator is synchronized and then directly connected to ac o. the synchronization introduces a delay of 1 - 2 clock cycles. ? bit 4 ? aci: analog comparator interrupt flag this bit is set by hardware when a comparator output event triggers the interrupt mode defined by acis1 and acis0. the analog comparator interrupt routine is executed if the acie bit is set and the i-bit in sreg is set. aci is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, aci is cleared by writing a logic one to the flag. 1 0 100 adc4 1 0 101 adc5 1 0 110 adc6 1 0 111 adc7 table 23-1. analog comparator multiplexed input (continued) acme aden mux2...0 analog co mparator negative input bit 7 6543210 (0x7b) ?acme ? ? ? adts2 adts1 adts0 adcsrb read/write r r/w r r r r/w r/w r/w initial value 0 0000000 bit 76543210 0x30 (0x50) acd acbg aco aci acie acic acis1 acis0 acsr read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 n/a 0 0 0 0 0 241 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bit 3 ? acie: analog comparator interrupt enable when the acie bit is written logic one and the i-bit in the status register is set, the analog comparator interrupt is activated. when written logic zero, the interrupt is disabled. ? bit 2 ? acic: analog comparator input capture enable when written logic one, this bit enables the input capture function in timer/counter1 to be triggered by the analog comparator. the comparator output is in this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the timer/counter1 input capture interrupt. when written logic zero, no connection between the analog comparator and the input capture function exists. to make the comparator trigger the timer/counter1 input capture interrupt, the icie1 bit in the timer interrupt mask register (timsk1) must be set. ? bits 1, 0 ? acis1, acis0: analog comparator interrupt mode select these bits determine which comparator events that trigger the analog comparator interrupt. the different settings are shown in table 23-2 . when changing the acis1/acis0 bits, the analog comparator interrupt must be disabled by clearing its interrupt enable bit in the acsr register. otherwise an interrupt can occur when the bits are changed. 23.3.3 didr1 ? digital in put disable register 1 ? bit 7:2 ? reserved these bits are unused bits in the atmega48a/pa/ 88a/pa/168a/pa/328/p, and w ill always read as zero. ? bit 1, 0 ? ain1d, ain0d: ai n1, ain0 digita l input disable when this bit is written logic one, the digital input buffer on the ain1/0 pin is disabled. the corresponding pin reg- ister bit will always read as zero when th is bit is set. when an analog signal is applied to the ain1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the dig- ital input buffer. table 23-2. acis1/acis0 settings acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle. 01reserved 1 0 comparator interrupt on falling output edge. 1 1 comparator interrupt on rising output edge. bit 76543210 (0x7f) ??????ain1dain0ddidr1 read/write rrrrrrr/wr/w initial value 0 0 0 0 0 0 0 0 242 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 24. analog-to-dig ital converter 24.1 features ? 10-bit resolution ? 0.5 lsb integral non-linearity ? 2 lsb absolute accuracy ? 13 - 260s conversion time ? up to 76.9ksps (up to 15ksp s at maximum resolution) ? 6 multiplexed single ended input channels ? 2 additional multiplexed single ended input channels (tqfp and qfn/mlf package only) ? temperature sensor input channel ? optional left adjustment for adc result readout ? 0 - v cc adc input voltage range ? selectable 1.1v adc reference voltage ? free running or single conversion mode ? interrupt on adc conversion complete ? sleep mode noise canceler 24.2 overview the atmega48a/pa/88a/pa/168a/pa/328/p features a 10-bi t successive approximatio n adc. the adc is con- nected to an 8-channel analog multiplexer which allows eight single-ended voltage inputs constructed from the pins of port a. the single-ended voltage inputs refer to 0v (gnd). the adc contains a sample and hold circuit which ensures that the input voltage to the adc is held at a constant level during conversion. a block diagram of the adc is shown in figure 24-1 on page 243 . the adc has a separate analog supply voltage pin, av cc . av cc must not differ more than 0.3v from v cc . see the paragraph ?adc noise canceler? on page 248 on how to connect this pin. internal reference voltages of nominally 1.1v or av cc are provided on-chip. the voltage reference may be exter- nally decoupled at the aref pin by a capacitor for better noise performance. the power reduction adc bit, pradc, in ?minimizing power cons umption? on page 41 must be disabled by writ- ing a logical zero to enable the adc. the adc converts an analog input voltage to a 10-bit di gital value through successive approximation. the mini- mum value represents gnd and the maximum value represents the voltage on the aref pin minus 1 lsb. optionally, av cc or an internal 1.1v reference voltage may be connected to the aref pin by writing to the refsn bits in the admux register. the internal voltage referenc e may thus be decoupled by an external capacitor at the aref pin to improve noise immunity. 243 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 24-1. analog to digital converter block schematic operation, the analog input channel is selected by writing to the mu x bits in admux. any of the adc input pins, as well as gnd and a fixed bandgap voltage reference, can be selected as single ended inputs to the adc. the adc is enabled by setting the adc enable bi t, aden in adcsra. volt age reference and input channel selections will not go into effect until aden is set. the adc does not consume power when aden is cleared, so it is recommended to switch off the adc before entering power saving sleep modes. the adc generates a 10-bit result which is presented in the adc data re gisters, adch and adcl. by default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the adlar bit in admux. if the result is left adjusted and no more than 8-bit precisio n is required, it is sufficie nt to read adch. otherwise, adcl must be read first, then adch, to ensure that the content of the data registers bel ongs to the same conver- sion. once adcl is read, adc access to data registers is blocked. this means that if adcl has been read, and a conversion completes before adch is read, neither register is updated and the result from the conversion is lost. when adch is read, adc access to the adch and adcl registers is re-enabled. adc conversion complete irq 8-bit data bus 15 0 adc multiplexer select (admux) adc ctrl. & status register (adcsra) adc data register (adch/adcl) mux2 adie adfr adsc aden adif adif mux1 mux0 adps0 adps1 adps2 mux3 conversion logic 10-bit dac + - sample & hold comparator internal 1.1v reference mux decoder avcc adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 refs0 refs1 adlar channel selection adc[9:0] adc multiplexer output aref bandgap reference prescaler gnd input mux temperature sensor 244 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 the adc has its own interrupt which can be triggered when a conversion completes. when adc access to the data registers is prohib ited between reading of adch an d adcl, the interrupt will trigger even if the result is lost. 24.3 starting a conversion a single conversion is started by disabling the power reduction adc bit, pradc, in ?minimizing power consump- tion? on page 41 by writing a logical zero to it and writing a logical one to the adc start conversion bit, adsc. this bit stays high as long as the conversion is in progress and will be cleare d by hardware when the conversion is com- pleted. if a different data channel is selected while a conversion is in pr ogress, the adc will finish the current conversion before performing the channel change. alternatively, a conversion can be triggered automatically by various sources. auto triggering is enabled by setting the adc auto trigger enable bit, adate in adcsra. the tr igger source is selected by setting the adc trigger select bits, adts in adcsrb (see description of the ad ts bits for a list of the trigger sources). when a positive edge occurs on the selected trigger signal, the adc prescale r is reset and a conversion is started. this provides a method of starting conversions at fixed intervals. if the trigger signal still is set when the conversion completes, a new conversion will not be star ted. if another positive ed ge occurs on the trigger signal during conversion, the edge will be ignored. note that an interrupt flag will be se t even if the specific interrupt is disabled or the global interrupt enable bit in sreg is cleared. a conversion can thus be triggered without causing an interrupt. however, the inter- rupt flag must be cleared in order to trigger a new conversion at the next interrupt event. figure 24-2. adc auto trigger logic using the adc interrupt flag as a trigger source make s the adc start a new conversion as soon as the ongoing conversion has finished. the adc then operates in free running mode, constantly sampling and updating the adc data register. the first conversion must be started by writing a logical one to the adsc bit in adcsra. in this mode the adc will perform successi ve conversions independen tly of whether the adc interrupt flag, adif is cleared or not. if auto triggering is enabled, single conversions can be started by writing adsc in adcsra to one. adsc can also be used to determine if a conversion is in progres s. the adsc bit will be r ead as one duri ng a conversion, independently of how the conversion was started. adsc adif source 1 source n adts[2:0] conversion logic prescaler start clk adc . . . . edge detector adate 245 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 24.4 prescaling and conversion timing figure 24-3. adc prescaler by default, the successive approximation circuitry requi res an input clock frequency between 50khz and 200khz to get maximum resolution. if a lower resolution than 10 bi ts is needed, the input clock frequency to the adc can be higher than 200khz to get a higher sample rate. the adc module contains a prescaler, which generates an acceptable adc clock fr equency from any cpu fre- quency above 100khz. the prescaling is set by the adps bits in adcsra. the prescaler starts counting from the moment the adc is switched on by setting the aden bit in adcsra. the prescaler keeps running for as long as the aden bit is set, and is continuously reset when aden is low. when initiating a single ended conversion by setting the ad sc bit in adcsra, the conversion starts at the follow- ing rising edge of the adc clock cycle. a normal conversion takes 13 adc clo ck cycles. the first conver sion after the adc is s witched on (aden in adc- sra is set) takes 25 adc clock cycles in order to initialize the analog circuitry. when the bandgap reference volt age is used as input to the adc, it will ta ke a certain time for the voltage to stabi- lize. if not stabilized, the fi rst value read after the firs t conversion may be wrong. the actual sample-and-hold takes place 1.5 adc clock cycl es after the start of a normal conversion and 13.5 adc clock cycles after the start of an first conversion. when a c onversion is complete, the result is written to the adc data registers, and adif is set. in single conversion mode, adsc is cleared simultaneously. the software may then set adsc again, and a new conversion will be initia ted on the first rising adc clock edge. when auto triggering is used, the prescaler is reset when the trigger event occurs. this assures a fixed delay from the trigger event to the start of co nversion. in this mode, the sample-and-hold ta kes place two adc clock cycles after the rising edge on the trigger source signal. three additional cpu clock cycles are used for synchronization logic. in free running mode, a new conver sion will be started immedi ately after the conversion completes, while adsc remains high. for a summary of conversion times, see table 24-1 on page 247 . 7-bit adc prescaler adc clock source ck adps0 adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 reset aden start 246 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 24-4. adc timing diagram, first conver sion (single conversion mode) figure 24-5. adc timing diagram, single conversion figure 24-6. adc timing diagram, auto triggered conversion sign and msb of result lsb of result adc clock adsc sample & hold adif adch adcl cycle number aden 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 first conversion next conversion 3 mux and refs update mux and refs update conversion complete 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 3 sample & hold mux and refs update conversion complete mux and refs update 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result adc clock trigger source adif adch adcl cycle number 12 one conversion next conversion conversion complete prescaler reset adate prescaler reset sample & hold mux and refs update 247 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 24-7. adc timing diagram, free running conversion 24.5 changing channel or reference selection the muxn and refs1:0 bits in the admux register are single buffered through a temporary register to which the cpu has random access. this ensures that the channels and reference selection only takes place at a safe point during the conversion. the channel and reference selectio n is continuously updated until a conversion is started. once the conversion starts, the channel and reference selectio n is locked to ensure a sufficient sampling time for the adc. continuous updating resumes in the last adc clock cycle before the conversion completes (adif in adcsra is set). note that the conversion starts on the following rising adc clock edge after adsc is written. the user is thus advised not to write new channel or refe rence selection values to admux until one adc clock cycle after adsc is written. if auto triggering is used, the exact time of the triggerin g event can be indeterministic. special care must be taken when updating the admux register, in order to control which conversion w ill be affected by the new settings. if both adate and aden is written to one, an interrupt event can occur at any time. if the admux register is changed in this period, the user cannot tell if the next co nversion is based on the old or the new settings. admux can be safely updated in the following ways: a. when adate or aden is cleared. b. during conversion, minimum one adc clock cycle after the trigger event. c. after a conversion, before the interrupt flag used as trigger source is cleared. when updating admux in one of th ese conditions, the new settings will affect the next adc conversion. 24.5.1 adc input channels when changing channel selections, the user should observe the following guid elines to ensure that the correct channel is selected: table 24-1. adc conversion time condition sample & hold (cycles from start of conversion) conversion time (cycles) first conversion 13.5 25 normal conversions, single ended 1.5 13 auto triggered conversions 2 13.5 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 34 conversion complete sample & hold mux and refs update 248 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 in single conversion mode, always select the channel befor e starting the conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. ho wever, the simplest method is to wait for the con- version to complete before changing the channel selection. in free running mode, always select the channel before st arting the first conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the first conversion to complete, and then change the channel selection. since the next conversion has already started automatically, the next result will reflect the previous channel selection. subsequent conversions will reflect the new channel selection. 24.5.2 adc voltage reference the reference voltage for the adc (v ref ) indicates the conversion range for the adc. single ended channels that exceed v ref will result in codes close to 0x3ff. v ref can be selected as either av cc , internal 1.1v reference, or external aref pin. av cc is connected to the adc through a passive switch. the internal 1.1v reference is generated from the internal bandgap reference (v bg ) through an internal amplifier. in either case, the external aref pin is directly connected to the adc, and the reference voltage can be made more immune to noise by connecting a capacitor between the aref pin and ground. v ref can also be measured at the aref pin with a high impedance voltmeter. note that v ref is a high impedance source, and only a capac itive load should be connected in a system. if the user has a fixed voltage source connected to the aref pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. if no external voltage is applied to the aref pin, the user may switch between av cc and 1.1v as reference selection. the first adc conversion result after switching reference voltage source may be inaccura te, and the user is advised to discard this result. 24.6 adc noise canceler the adc features a noise canceler that enables conversion during sleep m ode to reduce noise induced from the cpu core and other i/o peripherals. the noise canceler can be used with adc noise reduction and idle mode. to make use of this feature, the following procedure should be used: a. make sure that the adc is enabled and is not busy converting. single conversion mode must be selected and the adc conversion complete interrupt must be enabled. b. enter adc noise reduction mode (or idle mode). the adc will start a conversion once the cpu has been halted. c. if no other interrupts occur before the adc conv ersion completes, the adc interrupt will wake up the cpu and execute the adc conversion complete interrupt routine. if another interrupt wakes up the cpu before the adc conversion is complete, that interrupt will be executed, and an adc conversion complete interrupt request will be generated when the adc conversion completes. the cpu will remain in active mode until a new sleep command is executed. note that the adc will not be automatically turned off when entering other sleep modes than idle mode and adc noise reduction mode. the user is advised to write zero to aden before entering such sleep modes to avoid excessive power consumption. 24.6.1 analog input circuitry the analog input circuitry for single end ed channels is illustrated in figure 24- 8. an analog source applied to adcn is subjected to the pin capacitance and input leakage of t hat pin, regardless of whether that channel is selected as input for the adc. when the channel is selected, the sour ce must drive the s/h capacitor through the series resis- tance (combined resistance in the input path). the adc is optimized for analog signals with an output impedance of approximately 10 k ? or less. if such a source is used, the sampling time will be negligible. if a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the s/h capacitor, with can vary widely. the user is recom- 249 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 mended to only use low impedance sources with slowly vary ing signals, since this mi nimizes the required charge transfer to the s/h capacitor. signal components higher than the nyquist frequency (f adc /2) should not be present for either kind of channels, to avoid distortion from unpredictable si gnal convolution. the user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the adc. figure 24-8. analog input circuitry 24.6.2 analog noise canceling techniques digital circuitry inside and outside the device generates emi which might affect the accuracy of analog measure- ments. if conversion accuracy is critical, the noise leve l can be reduced by applying the following techniques: a. keep analog signal paths as short as possible. make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. b. the av cc pin on the device should be connected to the digital v cc supply voltage via an lc network as shown in figure 24-9 . c. use the adc noise canceler function to reduce induced noise from the cpu. d. if any adc [3:0] port pins are used as digital outputs, it is essential that these do not switch while a con- version is in progress. however, using the 2-wi re interface (adc4 and adc5) will only affect the conversion on adc4 and adc5 and not the other adc channels. adcn i ih 1..100 k c s/h = 14 pf v cc /2 i il 250 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 24-9. adc power connections 24.6.3 adc accuracy definitions an n-bit single-ended adc converts a voltage linearly between gnd and v ref in 2 n steps (lsbs). the lowest code is read as 0, and the highest code is read as 2 n -1. several parameters describe the deviation from the ideal behavior: ? offset: the deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 lsb). ideal value: 0 lsb. figure 24-10. offset error gnd vcc pc5 (adc5/scl) pc4 (adc4/sda) pc3 (adc3) pc2 (adc2) pc1 (adc1) pc0 (adc0) adc7 gnd aref avcc adc6 pb5 10 h 100nf analog ground plane output code v ref input voltage ideal adc actual adc offset error 251 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? gain error: after adjusting for offset, the gain error is found as the deviation of the last transition (0x3fe to 0x3ff) compared to the ideal transition (at 1.5 lsb below maximum). ideal value: 0 lsb figure 24-11. gain error ? integral non-linearity (inl): after adjusting for offset and gain error, the inl is the maximum deviation of an actual transition compared to an ideal transition for any code. ideal value: 0 lsb. figure 24-12. integral non- linearity (inl) ? differential non-linearity (dnl): the maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 lsb). ideal value: 0 lsb. output code v ref input voltage ideal adc actual adc gain error output code v ref input voltage ideal adc actual adc inl 252 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 24-13. differential non-linearity (dnl) ? quantization error: due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 lsb wide) will code to the same value. always 0.5 lsb. ? absolute accuracy: the maximum deviation of an actual (u nadjusted) transition compared to an ideal transition for any code. this is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. ideal value: 0.5 lsb. 24.7 adc conversion result after the conversion is complete (adif is high), the co nversion result can be found in the adc result registers (adcl, adch). for single ended conversion, the result is where v in is the voltage on the selected input pin and v ref the selected voltage reference (see table 24-3 on page 254 and table 24-4 on page 255 ). 0x000 represents analog ground, and 0x3ff represents the selected reference voltage minus one lsb. 24.8 temperature measurement the temperature measurement is based on an on-chip temperature sensor that is coupled to a single ended adc8 channel. selecting the adc8 channel by writing the mux3...0 bits in admux register to "1000" enables the tem- perature sensor. the internal 1.1v voltage reference must also be selected for the adc voltage reference source in the temperature sensor measurement. when the temperature sensor is enabled, the adc converter can be used in single conversion mode to measure the voltage over the temperature sensor. the measured voltage has a linear relationship to the temperature as described in table 24-2 . the voltage sensi- tivity is approximately 1 mv/c and the accura cy of the temperature measurement is +/- 10c. the values described in table 24-2 are typical values. however, due to the process variation the temperature sen- sor output voltage varies from one chip to another. to be capable of achieving more accurate results the output code 0x3ff 0x000 0 v ref input voltage dnl 1 lsb adc v in 1024 ? v ref -------------------------- = table 24-2. temperature vs. sensor output voltage (typical case) temperature / ? c-45 ? c+25 ? c+85 ? c voltage / mv 242mv 314mv 380mv 253 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 temperature measurement can be calibrated in the application software. the software calibration requires that a calibration value is measured and stored in a register or eeprom for each chip, as a part of the production test. the software calibration can be done utilizin g the formula: t = { [(adch << 8) | adcl] - t os } / k where adcn are the adc data registers, k is a fixed coefficient and t os is the temperature sensor offset value determined and st ored into eeprom as a part of the production test. 254 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 24.9 register description 24.9.1 admux ? adc multiplexer selection register ? bit 7:6 ? refs[1:0]: reference selection bits these bits select the voltage reference for the adc, as shown in table 24-3 . if these bits are changed during a conversion, the change will not go in effe ct until this conversion is complete (adif in adcsra is set). the internal voltage reference options may not be used if an external reference voltage is being applied to the aref pin. ? bit 5 ? adlar: adc left adjust result the adlar bit affects the presentation of the adc conv ersion result in the adc data register. write one to adlar to left adjust the resu lt. otherwise, the result is right adjust ed. changing the adlar bit will affect the adc data register immediately, regardless of any ongoing co nversions. for a complete de scription of this bit, see ?adcl and adch ? the adc data register? on page 256 . ? bit 4 ? reserved this bit is an unused bit in t he atmega48a/pa/88a/pa/1 68a/pa/328/p, and will always read as zero. ? bits 3:0 ? mux[3:0]: analog channel selection bits the value of these bits selects which analog inputs are connected to the adc. see table 24-4 for details. if these bits are changed during a conversion, the change will not go in effect until this conversion is complete (adif in adcsra is set). bit 76543210 (0x7c) refs1 refs0 adlar ? mux3 mux2 mux1 mux0 admux read/write r/w r/w r/w r r/w r/w r/w r/w initial value00000000 table 24-3. voltage reference selections for adc refs1 refs0 voltage reference selection 0 0 aref, internal v ref turned off 01 av cc with external capacitor at aref pin 10reserved 1 1 internal 1.1v voltage reference with external capacitor at aref pin 255 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. for temperature sensor. 24.9.2 adcsra ? adc control and status register a ? bit 7 ? aden: adc enable writing this bit to one enables the adc. by writing it to zero, th e adc is turned off. turning the adc off while a con- version is in progress, will terminate this conversion. ? bit 6 ? adsc: adc start conversion in single conversion mode, write this bit to one to start each conversion. in free running mode, write this bit to one to start the first conversion. the first conversion af ter adsc has been written after the adc has been enabled, or if adsc is written at the same ti me as the adc is enabled, will take 25 adc clock cycles instead of the normal 13. this first conversion perf orms initializat ion of the adc. adsc will read as one as long as a conv ersion is in progress. when the conver sion is complete, it returns to zero. writing zero to this bit has no effect. ? bit 5 ? adate: adc auto trigger enable when this bit is written to one, auto triggering of the adc is en abled. the adc will start a conversion on a positive edge of the selected trigger signal. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb. table 24-4. input channel selections mux3...0 single ended input 0000 adc0 0001 adc1 0010 adc2 0011 adc3 0100 adc4 0101 adc5 0110 adc6 0111 adc7 1000 adc8 (1) 1001 (reserved) 1010 (reserved) 1011 (reserved) 1100 (reserved) 1101 (reserved) 1110 1.1v (v bg ) 1111 0v (gnd) bit 76543210 (0x7a) aden adsc adate adif adie adps2 adps1 adps0 adcsra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 256 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bit 4 ? adif: adc interrupt flag this bit is set when an adc conversion completes and the data registers are updated. the adc conversion complete interrupt is executed if the adie bit and the i- bit in sreg are set. adif is cleared by hardware when executing the corresponding interrupt handling vector. alternat ively, adif is cleared by writing a logical one to the flag. beware that if doing a read-modify-write on adcsra, a pending interrupt can be disabled. this also applies if the sbi and cbi instructions are used. ? bit 3 ? adie: adc interrupt enable when this bit is written to one and the i-bit in sreg is set, the adc conversion complete interrupt is activated. ? bits 2:0 ? adps[2:0]: adc prescaler select bits these bits determine the division factor between the system clock frequency and the input clock to the adc. 24.9.3 adcl and adch ? the adc data register 24.9.3.1 adlar = 0 24.9.3.2 adlar = 1 when an adc conversion is complete, the result is found in these two registers. table 24-5. adc prescaler selections adps2 adps1 adps0 division factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 111 128 bit 151413121110 9 8 (0x79) ?????? adc9 adc8 adch (0x78) adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl 76543210 read/write rrrrrrrr rrrrrrrr initial value00000000 00000000 bit 151413121110 9 8 (0x79) adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch (0x78) adc1 adc0 ? ? ? ? ? ? adcl 76543210 read/write rrrrrrrr rrrrrrrr initial value 0 0 0 0 0 0 0 0 00000000 257 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 when adcl is read, the adc data register is not updated until adch is read. consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch. the adlar bit in admux, and the muxn bits in admux affect the way the result is read from the registers. if adlar is set, the result is left adjusted. if adlar is cleared (default), the result is right adjusted. ? adc9:0: adc conversion result these bits represent the result from the conversion, as detailed in ?adc conversion result? on page 252 . 24.9.4 adcsrb ? adc control and status register b ? bit 7, 5:3 ? reserved these bits are reserved for future use. to ensure compatibility with futu re devices, these bits must be written to zero when adcsrb is written. ? bit 2:0 ? adts[2:0]: adc auto trigger source if adate in adcsra is written to on e, the value of these bits selects wh ich source will trigger an adc conversion. if adate is cleared, the adts[2:0] se ttings will have no effect. a conversion will be triggered by the rising edge of the selected interrupt flag. note that switching from a trigge r source that is cleared to a trigger source that is set, will generate a positive e dge on the trigger signal. if aden in adcsra is set, this will start a conversion. switching to free running mode (adts[2:0]=0) will not cause a trigger event, even if the adc interrupt flag is set . 24.9.5 didr0 ? digital in put disable register 0 ? bits 7:6 ? reserved these bits are reserved for future use. to ensure compatibility with futu re devices, these bits must be written to zero when didr0 is written. bit 7 6543210 (0x7b) ? acme ? ? ? adts2 adts1 adts0 adcsrb read/write r r/w r r r r/w r/w r/w initial value 0 0000000 table 24-6. adc auto trigger source selections adts2 adts1 adts0 trigger source 0 0 0 free running mode 0 0 1 analog comparator 0 1 0 external interrupt request 0 0 1 1 timer/counter0 compare match a 1 0 0 timer/counter0 overflow 1 0 1 timer/counter1 compare match b 1 1 0 timer/counter1 overflow 1 1 1 timer/counter1 capture event bit 76543210 (0x7e) ? ? adc5d adc4d adc3d adc2d adc1d adc0d didr0 read/write r r r/w r/w r/w r/w r/w r/w initial value00000000 258 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bit 5:0 ? adc5d...adc0d: adc5...0 digital input disable when this bit is written logic one, the digital input bu ffer on the corresponding adc pin is disabled. the corre- sponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the adc5...0 pin and the digital input from this pin is no t needed, this bit should be written logic one to reduce power consumption in the digital input buffer. note that adc pins adc7 and adc6 do not have digita l input buffers, and therefore do not require digital input disable bits. 259 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 25. debugwire on-chip debug system 25.1 features ? complete program flow control ? emulates all on-chip functions, both digital and analog, except reset pin ? real-time operation ? symbolic debugging support (both at c and as sembler source level, or for other hlls) ? unlimited number of program break po ints (using software break points) ? non-intrusive operation ? electrical characteristics identical to real device ? automatic configuration system ? high-speed operation ? programming of non-volatile memories 25.2 overview the debugwire on-chip debug system uses a one-wire, bi-d irectional interface to control the program flow, exe- cute avr instructions in the cpu and to program the different non-volatile memories. 25.3 physical interface when the debugwire enable (dwen) fuse is progra mmed and lock bits are unprogrammed, the debugwire system within the target device is activated. the reset po rt pin is configured as a wire-and (open-dra in) bi-direc- tional i/o pin with pull-up enabled and becomes the communication gateway between target and emulator. figure 25-1. the debugwire setup figure 25-1 shows the schematic of a target mcu, with debugwire enabled, and the emulator connector. the system clock is not affect ed by debugwire and will always be the clock source selected by the cksel fuses. when designing a system where debugwire will be used, the following observations must be made for correct operation: dw gnd dw(reset) vcc 1.8 - 5.5v 260 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? pull-up resistors on the dw/(reset) line must not be smaller than 10k ? . the pull-up resistor is not required for debugwire functionality. ? connecting the reset pin directly to v cc will not work. ? capacitors connected to the reset pin must be disc onnected when us ing debugwire. ? all external reset sources must be disconnected. 25.4 software break points debugwire supports program memory break points by the avr break instruction. setting a break point in avr studio ? will insert a break instru ction in the program memory. the instru ction replaced by the break instruction will be stored. when program execution is continued, the stored inst ruction will be executed before continuing from the program memory. a break can be insert ed manually by putting the br eak instruction in the program. the flash must be re-programmed each time a break point is changed. this is automatically handled by avr stu- dio through the debugwire in terface. the use of break points will th erefore reduce the flash data retention. devices used for debugging purposes should not be shipped to end customers. 25.5 limitations of debugwire the debugwire communication pin (dw) is physically located on the same pi n as external reset (reset). an external reset source is therefore not supported when the debugwire is enabled. a programmed dwen fuse enables some parts of the clock system to be running in all sleep modes. this will increase the power consumption while in sleep. thus, th e dwen fuse should be disabled when debugwire is not used. 25.6 register description the following section describes the registers used with the debugwire. 25.6.1 dwdr ? debugwire data register the dwdr register provides a co mmunication channel from the running program in the mcu to the debugger. this register is only accessible by the debugwire and ca n therefore not be used as a general purpose register in the normal operations. bit 76543210 dwdr[7:0] dwdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 261 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 26. self-programming the flash, atmega 48a/48pa 26.1 overview in atmega 48a/48pa there is no read-while-write support, and no separate boot loader section. the spm instruction can be executed from the entire flash. the device provides a self-programming mechanism fo r downloading and uploading program code by the mcu itself. the self-programming can use any available data in terface and associated protocol to read code and write (program) that code into the program memory. the program memory is updated in a page by page fashion. before programming a page with the data stored in the temporary page bu ffer, the page must be erased. the temporary page buffer is filled one word at a time using spm and the buffer can be filled either before the page erase command or between a page erase and a page write operation: alternative 1, fill the bu ffer before a page erase ? fill temporary page buffer ? perform a page erase ? perform a page write alternative 2, fill the buffer after page erase ? perform a page erase ? fill temporary page buffer ? perform a page write if only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be re-written. when using alternative 1, the boot loader provides an effec- tive read-modify-write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. if alternative 2 is us ed, it is not possible to read the old data while loading since the page is already erased. the temporary page buffer can be accessed in a random sequence. it is essen- tial that the page address used in both the page erase and page write operation is addressing the same page. 26.1.1 performing page erase by spm to execute page erase, set up the address in the z-pointer, write ?00000011? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be writ- ten to pcpage in the z-register . other bits in the z-pointer will be ignored during this operation. ? the cpu is halted during the page erase operation. note: if an interrupt occurs in the time sequence the four cycl e access cannot be guaranteed. in order to ensure atomic oper- ation you should disable interrupts before writing to spmcsr. 26.1.2 filling the temporary buffer (page loading) to write an instructio n word, set up the address in the z-pointer and data in r1:r0, write ?00000001? to spmcsr and execute spm within four clock cycles after writing sp mcsr. the content of pcword in the z-register is used to address the data in the temporary buffer. the temporar y buffer will auto-era se after a page write operation or by writing the rwwsre bit in spmcsr. it is also erased after a system reset. note that it is not possible to write more than one time to each address without erasing the temporary buffer. if the eeprom is written in the middle of an spm page load operation, all dat a loaded will be lost. 262 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 26.1.3 performing a page write to execute page write, set up the address in the z-poi nter, write ?00000101? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 an d r0 is ignored. the page address must be written to pcpage. other bits in the z-pointer must be written to zero during this operation. ? the cpu is halted during the page write operation. 26.2 addressing the flash during self-programming the z-pointer is used to address the spm commands. since the flash is organized in pages (see table 28-11 on page 290 ), the program counter can be treated as hav- ing two different sections. one section, consisting of t he least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. this is shown in figure 27-3 on page 274 . note that the page erase and page write operations are addressed independently. therefore it is of major importance that the software addresses the same page in both the page erase and page write operation. the lpm instruction uses the z-pointer to store the addr ess. since this instruction addresses the flash byte-by- byte, also the lsb (bit z0) of the z-pointer is used. figure 26-1. addressing the flash during spm (1) note: 1. the different variables used in figure 27-3 are listed in table 28-11 on page 290 . 26.2.1 eeprom write prevents writing to spmcsr note that an eeprom write operation will block all software programming to flash. reading the fuses and lock bits from software will also be prevented during the e eprom write operati on. it is recomm ended that the user checks the status bit (eepe) in the eecr register and verifies th at the bit is cleared bef ore writing to the spmcsr register. bit 151413121110 9 8 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30) z7z6z5z4z3z2z1z0 76543210 program memory 0 1 15 z - register bit 0 zpagemsb word address within a page page address within the flash zpcmsb instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter 263 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 26.2.2 reading the fuse and lock bits from software it is possible to read both the fuse and lock bits from software. to read the lock bits, load the z-pointer with 0x0001 and set the blbset and spmen bits in spmcsr. when an lpm instruction is executed within three cpu cycles after the bl bset and spmen bits are set in spmcsr, the value of the lock bi ts will be loaded in the des- tination register. the blbset and spmen bits will auto-clear upon completion of reading the lock bits or if no lpm instruction is executed within three cpu cycles or no spm instruction is executed within four cpu cycles. when blbset and spmen are cleared, lpm will work as described in the in struction set manual. the algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. to read the fuse low byte, load the z- pointer with 0x0000 and se t the blbset and spmen bits in spmcsr. when an lpm instruction is executed within three cycles afte r the blbset and spmen bits are set in the spmcsr, the value of the fuse low byte (flb ) will be loaded in the destinatio n register as shown below.see table 28-5 on page 287 for a detailed description and mapping of the fuse low byte. similarly, when reading the fuse high byte (fhb), load 0x0003 in the z-pointer. when an lpm instruction is exe- cuted within three cycles after the blbset and spmen bits are set in the spmcsr, the value of the fuse high byte will be loaded in the destination register as shown below. see table 28-5 on page 287 for detailed description and mapping of the extended fuse byte. similarly, when reading the extended fuse byte (efb), l oad 0x0002 in the z-pointer. when an lpm instruction is executed within three cycles after the blbset and spmen bits are set in the spmcsr, the value of the extended fuse byte will be loaded in the dest ination register as shown below. see table 28-5 on page 287 for detailed description and mapping of the extended fuse byte. fuse and lock bits that are progra mmed, will be read as zero . fuse and lock bits that are unprogrammed, will be read as one. bit 76543210 rd ??????lb2lb1 bit 76543210 rd flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 bit 76543210 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 bit 76543210 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 264 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 26.2.3 preventing flash corruption during periods of low v cc , the flash program can be corrupted because the supply voltage is too low for the cpu and the flash to operate properly. these issues are the same as for board level systems using the flash, and the same design solutions should be applied. a flash program corruption can be caused by two situations when the voltage is too low. first, a regular write sequence to the flash requires a minimum voltage to operate correctly. secondly, the cpu itself can execute instructions incorrectly, if the supply vo ltage for executing inst ructions is too low. flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. keep the avr reset active (low) during periods of in sufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating voltage matches the detection level. if not, an external low v cc reset protection circuit can be used. if a reset occurs while a write operation is in prog- ress, the write operation will be completed provi ded that the power supply voltage is sufficient. 2. keep the avr core in power-down sleep mode during periods of low v cc . this will prevent the cpu from attempting to decode and execute instructions, effectively protecting the spmcsr register and thus the flash from unintentional writes. 26.2.4 programming time for flash when using spm the calibrated rc oscillator is used to time flash accesses. table 27-6 shows the typical programming time for flash accesses from the cpu. note: 1. minimum and maximum programming time is per individual operation. table 26-1. spm programming time (1) symbol min. programming time max programming time flash write (page erase, page write, and write lock bits by spm) 3.7ms 4.5ms 265 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 26.2.5 simple assembly code example for a boot loader note that the rwwsb bit will always be read as zero in atmega 48a/48pa. nevertheless, it is recommended to check this bit as shown in the code example, to en sure compatibility with devices supporting read-while-write. ;-the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by the y pointer ; the first data location in flash is pointed to by the z-pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the do_spm sub routine). only code inside nrww section can ; be read during self-programming (page erase and page write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-it is assumed that either the interrupt table is moved to the boot ; loader section or that the interrupts are disabled. .equ pagesizeb = pagesize*2 ;pagesizeb is page size in bytes, not words .org smallbootstart write_page: ; page erase ldi spmcrval, (1< 268 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bit 0 ? spmen: store program memory this bit enables the spm instruction for the next four clock cycles. if written to one together with either rwwsre, blbset, pgwrt, or pgers, the followin g spm instruction will have a special meaning, see description above. if only spmen is written, the following spm instruction will store the value in r1:r0 in the temporary page buffer addressed by the z-poin ter. the lsb of the z-pointer is ignored. the spmen bit will au to-clear upon completion of an spm instruction, or if no spm instruction is executed within four clock cycles. during page erase and page write, the spmen bit remains high until the operation is completed. writing any other combination than ?10001?, ?0 1001?, ?00101?, ?00011? or ? 00001? in the lower five bits will have no effect. 269 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 27. boot loader support ? read -while-write self-programming the boot loader support applies to atmega88a/88pa/168a/168pa/328/328p 27.1 features ? read-while-write self-programming ? flexible boot memory size ? high security (separate boot lock bits for a flexible protection) ? separate fuse to select reset vector ? optimized page (1) size ? code efficient algorithm ? efficient read-modify-write support note: 1. a page is a section in the flash consisting of several bytes (see table 28-11 on page 290 ) used during program- ming. the page organization does not affect normal operation. 27.2 overview in atmega88a/88pa/168a/168pa/328/328p the boot loader support provides a real read-while-write self-pro- gramming mechanism for downloading and uploading program code by the mcu itself. this feature allows flexible application software updates controlled by the mcu usin g a flash-resident boot loader program. the boot loader program can use any available data interface and associated protocol to read code and write (program) that code into the flash memory, or read the code from the program memory. the program code within the boot loader sec- tion has the capability to write into the entire flash, including the boot loader memory. the bo ot loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. the size of the boot loader memory is configurable with fuses and the boot loader has two separate sets of boot lock bits which can be set independently. this gives the user a unique flexib ility to select di fferent levels of protection. 27.3 application and boot loader flash sections the flash memory is organized in two main sections, th e application section and the boot loader section (see fig- ure 27-2 ). the size of the different sections is c onfigured by the bootsz fuses as shown in table 27-7 on page 280 and figure 27-2 . these two sections can have different level of protection since they have different sets of lock bits. 27.3.1 application section the application section is the section of the flash that is used for storing the application code. the protection level for the application section can be selected by the a pplication boot lock bits (boot lock bits 0), see table 27-2 on page 273 . the application section can never store any boot loader code since the spm instruction is disabled when executed from the application section. 27.3.2 bls ? boot loader section while the application section is used for storing the application code, the the boot loader software must be located in the bls since the spm instruction can initiate a programming when executing from the bls only. the spm instruction can access the entire flash, including the bls itself. the protection level for the boot loader sec- tion can be selected by the boot loader lock bits (boot lock bits 1), see table 27-3 on page 273 . 27.4 read-while-write and no r ead-while-write flash sections whether the cpu supports read-while-write or if the cpu is halted during a boot loader software update is dependent on which address that is being programmed. in add ition to the two sections that are configurable by the bootsz fuses as described above, the flash is also divided into two fixed sections, the read-while-write 270 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 (rww) section and the no read-while -write (nrww) section. the limit between the rww- and nrww sections is given in table 27-8 on page 280 and figure 27-2 on page 272 . the main difference between the two sections is: ? when erasing or writing a page located inside the rww section, the nrww section can be read during the operation. ? when erasing or writing a page located inside the nrww section, the cpu is halted during the entire operation. note that the user software can never read any code that is located inside the rww section during a boot loader software operation. the syntax ?read-while-write section? refers to which section that is being programmed (erased or written), not which section that actually is being read during a boot loader software update. 27.4.1 rww ? read-while-write section if a boot loader software update is programming a page inside the rww section, it is possible to read code from the flash, but only code that is located in the nrww section. during an on-going programming, the software must ensure that the rww section never is being read. if the user software is trying to read code that is located inside the rww section (i.e., by a call/jmp/lpm or an interrupt ) during programming, the software might end up in an unknown state. to avoid this, the inte rrupts should either be disabled or moved to the boot loader section. the boot loader section is always loca ted in the nrww section. the rww se ction busy bit (rwwsb) in the store program memory control and status r egister (spmcsr) will be read as logi cal one as long as the rww section is blocked for reading. after a programming is completed, the rwwsb must be cleared by software before reading code located in the rww section. see section ?27.9.1? on page 283. for details on how to clear rwwsb. 27.4.2 nrww ? no read-while-write section the code located in the nrww section can be read when the boot loader software is updating a page in the rww section. when the boot loader code updates the nrww section, the cpu is halted during the entire page erase or page write operation. table 27-1. read-while-write features which section does the z- pointer address during the programming? which section can be read during programming? cpu halted? read-while-write supported? rww section nrww section no yes nrww section none yes no 271 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 27-1. read-while-write vs. no read-while-write read-while-write (rww) section no read-while-write (nrww) section z-pointer addresses rww section z-pointer addresses nrww section cpu is halted during the operation code located in nrww section can be read during the operation 272 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 27-2. memory sections note: 1. the parameters in the figure above are given in table 27-7 on page 280 . 27.5 boot loader lock bits if no boot loader capability is needed, the entire flash is available fo r application code. th e boot loader has two separate sets of boot lock bits which can be set independ ently. this gives the user a unique flexibility to select dif- ferent levels of protection. the user can select: ? to protect the entire flash from a software update by the mcu. ? to protect only the boot loader flash section from a software update by the mcu. ? to protect only the application flash section from a software update by the mcu. ? allow software update in the entire flash. see table 27-2 and table 27-3 for further details. the boot lock bits can be set in software and in serial or paral- lel programming mode, but they can be cleared by a chip erase command only. the general write lock (lock bit mode 2) does not control the programming of the flas h memory by spm instruction. similarly, the general read/write lock (lock bit mode 1) does not control reading nor writing by lpm/spm, if it is attempted. 0x0000 flashend program memory bootsz = '11' application flash section boot loader flash section flashend program memory bootsz = '10' 0x0000 program memory bootsz = '01' program memory bootsz = '00' application flash section boot loader flash section 0x0000 flashend application flash section flashend end rww start nrww application flash section boot loader flash section boot loader flash section end rww start nrww end rww start nrww 0x0000 end rww, end application start nrww, start boot loader application flash section application flash section application flash section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section end application start boot loader end application start boot loader end application start boot loader 273 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. ?1? means unprogrammed, ?0? means programmed note: 1. ?1? means unprogrammed, ?0? means programmed 27.6 entering the b oot loader program entering the boot loader takes place by a jump or call from the application program. this may be initiated by a trig- ger such as a command received via usart, or spi in terface. alternatively, the boot reset fuse can be programmed so that the reset vector is pointing to the boot flash start address after a reset. in this case, the boot loader is started after a reset. after the application code is loaded, the program can start executing the application code. note that the fuses cannot be changed by the mcu itself. this means that once the boot reset fuse is pro- grammed, the reset vector will always point to the boot loader reset an d the fuse can only be changed through the serial or parallel programming interface. note: 1. ?1? means unprogrammed, ?0? means programmed table 27-2. boot lock bit0 protection modes (application section) (1) blb0 mode blb02 blb01 protection 111 no restrictions for spm or lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 300 spm is not allowed to write to the application section, and lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 401 lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. table 27-3. boot lock bit1 protection modes (boot loader section) (1) blb1 mode blb12 blb11 protection 111 no restrictions for spm or lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to the boot loader section, and lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 401 lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. table 27-4. boot reset fuse (1) bootrst reset address 1 reset vector = application reset (address 0x0000) 0 reset vector = boot loader reset (see table 27-7 on page 280 ) 274 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 27.7 addressing the flash during self-programming the z-pointer is used to address the spm commands. since the flash is organized in pages (see table 28-11 on page 290 ), the program counter can be treated as hav- ing two different sections. one section, consisting of t he least significant bits, is addressing the words within a page, while the most significant bits ar e addressing the pages. this is1 shown in figure 27-3 . note that the page erase and page write operations are addressed independently . therefore it is of major importance that the boot loader software addresses the same page in both the page erase and page write operation. once a program- ming operation is initiated, the address is latched and the z-pointer can be used for other operations. the only spm operation that does not use the z-pointer is setting the boot loader lock bits. the content of the z- pointer is ignored and will have no effect on the operation. the lpm instruction does also use the z-pointer to store the address. since this instruction addresses the flash byte-b y-byte, also the lsb (bit z0) of the z-pointer is used. figure 27-3. addressing the flash during spm (1) note: 1. the different variables used in figure 27-3 are listed in table 27-9 on page 280 . bit 151413121110 9 8 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30) z7z6z5z4z3z2z1z0 76543210 program memory 0 1 15 z - register bit 0 zpagemsb word address within a page page address within the flash zpcmsb instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter 275 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 27.8 self-programming the flash the program memory is updated in a page by page fashion. before programming a page with the data stored in the temporary page buffer, t he page must be erased . the temporary pa ge buffer is filled one wo rd at a time using spm and the buffer can be filled either before the page erase command or between a page erase and a page write operation: alternative 1, fill the bu ffer before a page erase ? fill temporary page buffer ? perform a page erase ? perform a page write alternative 2, fill the buffer after page erase ? perform a page erase ? fill temporary page buffer ? perform a page write if only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. w hen using alternative 1, the boot loader provides an effec- tive read-modify-write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. if alternative 2 is us ed, it is not possible to read the old data while loading since the page is already erased. the temporary page buffer can be accessed in a random sequence. it is essen- tial that the page address used in both the page erase and page write operation is addressing the same page. see ?simple assembly code example for a boot loader? on page 278 for an assembly code example. 27.8.1 performing page erase by spm to execute page erase, set up the address in the z-pointer, write ?x0000011? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be writ- ten to pcpage in the z-register . other bits in the z-pointer will be ignored during this operation. ? page erase to the rww section: the nrww section can be read during the page erase. ? page erase to the nrww section: the cpu is halted during the operation. 27.8.2 filling the temporary buffer (page loading) to write an instructio n word, set up the address in the z-pointer and data in r1:r0, write ?00000001? to spmcsr and execute spm within four clock cycles after writing sp mcsr. the content of pcword in the z-register is used to address the data in the temporary buffer. the temporar y buffer will auto-era se after a page write operation or by writing the rwwsre bit in spmcsr. it is also erased after a system reset. note that it is not possible to write more than one time to each address without erasing the temporary buffer. if the eeprom is written in the middle of an spm page load operation, all dat a loaded will be lost. 27.8.3 performing a page write to execute page write, set up the address in the z-pointer, write ?x0000101? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 an d r0 is ignored. the page address must be written to pcpage. other bits in the z-pointer must be written to zero during this operation. ? page write to the rww section: the nrww section can be read during the page write. ? page write to the nrww section: the cpu is halted during the operation. 27.8.4 using the spm interrupt if the spm interrupt is enabled, the spm interrupt will generate a constant interrupt when the spmen bit in spmcsr is cleared. this means that the interrupt can be used instead of polling the spmcsr register in soft- 276 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ware. when using the spm interrupt, the interrupt vector s should be moved to the bls section to avoid that an interrupt is accessing the rww section when it is block ed for reading. how to move the interrupts is described in ?interrupts? on page 57 . 27.8.5 consideration while updating bls special care must be taken if the user allows the b oot loader section to be updated by leaving boot lock bit11 unprogrammed. an accidental write to the boot loader itself can corrupt the entire boot loader, and further soft- ware updates might be impossible. if it is not necessary to change the boot loader software itself, it is recommended to program the boot lock bit11 to protect the boot loader software from any internal software changes. 27.8.6 prevent reading the rww section during self-programming during self-programming (either page erase or page write), the rww section is always blocked for reading. the user software itself must prevent that this section is addressed during the self programming operation. the rwwsb in the spmcsr will be set as long as the rww section is busy. during self-programming the interrupt vector table should be moved to the bls as described in ?watchdog timer? on page 50 , or the interrupts must be disabled. before addressing the rww section after the programming is completed, the user software must clear the rwwsb by writing the rwwsre. see ?simple assembly code example for a boot loader? on page 278 for an example. 27.8.7 setting the boot loader lock bits by spm to set the boot loader lock bits and general lock bits, write the desired data to r0, write ?x0001001? to spmcsr and execute spm within four clock cycles after writing spmcsr. see table 27-2 and table 27-3 for how the different settings of the boot loader bits affect the flash access. if bits 5...0 in r0 are cleared (zero), the corresponding lock bit will be programmed if an spm instruction is exe- cuted within four cycles after bl bset and spmen are set in spmcsr. the z-pointer is don?t care during this operation, but for future compatibility it is recommended to load the z-pointer with 0x 0001 (same as used for read- ing the lo ck bits). for future compatibility it is also recommend ed to set bits 7 and 6 in r0 to ?1? when writing the lock bits. when programming the lock bits the entire flash can be read during the operation. 27.8.8 eeprom write prevents writing to spmcsr note that an eeprom write operation will block all software programming to flash. reading the fuses and lock bits from software will also be prevented during the e eprom write operati on. it is recomm ended that the user checks the status bit (eepe) in the eecr register and verifies th at the bit is cleared bef ore writing to the spmcsr register. 27.8.9 reading the fuse and lock bits from software it is possible to read both the fuse and lock bits from software. to read the lock bits, load the z-pointer with 0x0001 and set the blbset and spmen bits in spmcsr. when an lpm instruction is executed within three cpu cycles after the bl bset and spmen bits are set in spmcsr, the value of the lock bi ts will be loaded in the des- tination register. the blbset and spmen bits will auto-clear upon completion of reading the lock bits or if no lpm instruction is executed within three cpu cycles or no spm instruction is executed within four cpu cycles. when blbset and spmen are cleared, lpm will work as described in the in struction set manual. the algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. to read the fuse low byte, load the z- pointer with 0x0000 and se t the blbset and spmen bits in spmcsr. when bit 76543210 r0 1 1 blb12 blb11 blb02 blb01 lb2 lb1 bit 76543210 rd ? ? blb12 blb11 blb02 blb01 lb2 lb1 277 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 an lpm instruction is executed within three cycles afte r the blbset and spmen bits are set in the spmcsr, the value of the fuse low byte (flb) will be loaded in the de stination register as shown below. refer to table 28-5 on page 287 for a detailed description and mapping of the fuse low byte. similarly, when reading the fuse high byte, load 0x0003 in the z-pointer. when an lpm instruction is executed within three cycles after the blbset and spmen bits ar e set in the spmcsr, the va lue of the fuse high byte (fhb) will be loaded in the destination register as shown below. refer to table 28-7 on page 287 for detailed description and mapping of the fuse high byte. when reading the extended fuse byte, load 0x0002 in the z-pointer. when an lpm instruction is executed within three cycles after the blbset and spmen bits are set in the spmcsr, the value of the extended fuse byte (efb) will be loaded in the destinatio n register as shown below. refer to table 28-5 on page 287 for detailed description and mapping of the extended fuse byte. fuse and lock bits that are progra mmed, will be read as zero . fuse and lock bits that are unprogrammed, will be read as one. 27.8.10 reading the signature row from software to read the signature row from software, load the z- pointer with the signature byte address given in table 27-5 on page 277 and set the sigrd and spmen bits in spmcsr. when an lpm instruction is executed within three cpu cycles after the sigrd and spmen bi ts are set in spmcsr, the signatur e byte value will be loaded in the destination register. the sigrd and spmen bits will auto-clear upon completion of reading the signature row lock bits or if no lpm instruction is executed within three cpu cycles. when sigrd and spmen are cleared, lpm will work as described in t he instruction set manual. note: all other addresses are reserved for future use. 27.8.11 preventing flash corruption during periods of low v cc , the flash program can be corrupted because the supply voltage is too low for the cpu and the flash to operate properly. these issues are the same as for board level systems using the flash, and the same design solutions should be applied. a flash program corruption can be caused by two situations when the voltage is too low. first, a regular write sequence to the flash requires a minimum voltage to operate correctly. secondly, the cpu itself can execute instructions incorrectly, if the supply vo ltage for executing inst ructions is too low. flash corruption can easily be avoided by following these design recommendations (one is sufficient): bit 76543210 rd flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 bit 76543210 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 bit 76543210 rd ? ? ? ? efb3 efb2 efb1 efb0 table 27-5. signature row addressing signature byte z-pointer address device signature byte 1 0x0000 device signature byte 2 0x0002 device signature byte 3 0x0004 rc oscillator calibration byte 0x0001 278 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 1. if there is no need for a boot loader update in the system, program the boot loader lock bits to prevent any boot loader software updates. 2. keep the avr reset active (low) during periods of in sufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating voltage matches the detection level. if not, an external low v cc reset protection circuit can be used. if a reset occurs while a write operation is in prog- ress, the write operation will be completed provi ded that the power supply voltage is sufficient. 3. keep the avr core in power-down sleep mode during periods of low v cc . this will prevent the cpu from attempting to decode and execute instructions, effectively protecting the spmcsr register and thus the flash from unintentional writes. 27.8.12 programming time for flash when using spm the calibrated rc oscillator is used to time flash accesses. table 27-6 shows the typical programming time for flash accesses from the cpu. note: 1. minimum and maximum programming time is per individual operation. 27.8.13 simple assembly code example for a boot loader ;-the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by the y pointer ; the first data location in flash is pointed to by the z-pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the do_spm sub routine). only code inside nrww section can ; be read during self-programming (page erase and page write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-it is assumed that either the interrupt table is moved to the boot ; loader section or that the interrupts are disabled. .equ pagesizeb = pagesize*2 ;pagesizeb is page size in bytes, not words .org smallbootstart write_page: ; page erase ldi spmcrval, (1< 281 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 27.8.15 atmega168a and atmega168pa boot loader parameters in table 27-10 through table 27-12 , the parameters used in the description of the self programming are given. note: the different bootsz fuse configurations are shown in figure 27-2 on page 272 . for details about these two section, see ?nrww ? no read-while-write section? on page 270 and ?rww ? read-while- write section? on page 270 note: 1. z15:z14: always ignored z0: should be zero for all spm commands, byte select for the lpm instruction. see ?addressing the flash during self-programming? on page 274 for details about the use of z-pointer during self- programming. table 27-10. boot size configuration, atmega168a/168pa bootsz1 bootsz0 boot size pages application flash section boot loader flash section end application section boot reset address (start boot loader section) 1 1 128 words 2 0x0000 - 0x1f7f 0x1f80 - 0x1fff 0x1f7f 0x1f80 1 0 256 words 4 0x0000 - 0x1eff 0x1f00 - 0x1fff 0x1eff 0x1f00 0 1 512 words 8 0x0000 - 0x1dff 0x1e00 - 0x1fff 0x1dff 0x1e00 0 0 1024 words 16 0x0000 - 0x1bff 0x1c00 - 0x1fff 0x1bff 0x1c00 table 27-11. read-while-write limit, atmega168a/168pa section pages address read-while-write section (rww) 112 0x0000 - 0x1bff no read-while-write section (nrww) 16 0x1c00 - 0x1fff table 27-12. explanation of different variables used in figure 27-3 and the mapping to the z-pointer, atmega168a/168pa variable corresponding z-value (1) description pcmsb 12 most significant bit in the prog ram counter. (the program counter is 13 bits pc[12:0]) pag e m s b 5 most significant bit which is us ed to address the words within one page (64 words in a page requires 6 bits pc [5:0]) zpcmsb z13 bit in z-register that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z6 bit in z-register that is mapped to pagemsb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[12:6] z13:z7 program counter page address: page select, for page erase and page write pcword pc[5:0] z6:z1 program counter word address: wo rd select, for filling temporary buffer (must be zero during page write operation) 282 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 27.8.16 atmega328 and atmega328p boot loader parameters in table 27-13 through table 27-15 , the parameters used in the description of the self programming are given. note: the different bootsz fuse configurations are shown in figure 27-2 on page 272 . for details about these two section, see ?nrww ? no read-while-write section? on page 270 and ?rww ? read-while- write section? on page 270 . note: 1. z15: always ignored z0: should be zero for all spm commands, byte select for the lpm instruction. see ?addressing the flash during self-programming? on page 274 for details about the use of z-pointer during self- programming. table 27-13. boot size configuration, atmega328/328p bootsz1 bootsz0 boot size pages application flash section boot loader flash section end application section boot reset address (start boot loader section) 1 1 256 words 4 0x0000 - 0x3eff 0x3f00 - 0x3fff 0x3eff 0x3f00 1 0 512 words 8 0x0000 - 0x3dff 0x3e00 - 0x3fff 0x3dff 0x3e00 0 1 1024 words 16 0x0000 - 0x3bff 0x3c00 - 0x3fff 0x3bff 0x3c00 0 0 2048 words 32 0x0000 - 0x37ff 0x3800 - 0x3fff 0x37ff 0x3800 table 27-14. read-while-write limit, atmega328/328p section pages address read-while-write section (rww) 224 0x0000 - 0x37ff no read-while-write section (nrww) 32 0x3800 - 0x3fff table 27-15. explanation of different variables used in figure 27-3 and the mapping to the z-pointer, atmega328/328p variable corresponding z-value (1) description pcmsb 13 most significant bit in the prog ram counter. (the program counter is 14 bits pc[13:0]) pag e m s b 5 most significant bit which is us ed to address the words within one page (64 words in a page requires 6 bits pc [5:0]) zpcmsb z14 bit in z-register that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z6 bit in z-register that is mapped to pagemsb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[13:6] z14:z7 program counter page address: page select, for page erase and page write pcword pc[5:0] z6:z1 program counter word address: wo rd select, for filling temporary buffer (must be zero during page write operation) 283 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 27.9 register description 27.9.1 spmcsr ? store program memory control and status register the store program memory control and status register contains the control bits needed to control the boot loader operations. ? bit 7 ? spmie: spm interrupt enable when the spmie bit is written to one, and the i-bit in the status register is set (one ), the spm ready interrupt will be enabled. the spm ready interrupt will be executed as long as the spmen bit in the spmcsr register is cleared. ? bit 6 ? rwwsb: read-while-write section busy when a self-programming (page erase or page write) operation to the r ww section is initiated, the rwwsb will be set (one) by hardware. when the rwwsb bit is set, the rww section cannot be accessed. the rwwsb bit will be cleared if the rwwsre bit is wri tten to one after a self-programming o peration is completed. alternatively the rwwsb bit will automatically be cleared if a page load oper ation is initiated. ? bit 5 ? sigrd: signature row read if this bit is written to one at the same time as spmen , the next lpm instruction within three clock cycles will read a byte from the signature row into the destination register. see ?reading the signature row from software? on page 277 for details. an spm instruction within four cycles after sigrd and spmen are set will have no effect. this operation is reserved for future use and should not be used. ? bit 4 ? rwwsre: read-while-write section read enable when programming (page erase or page write) to the rw w section, the rww section is blocked for reading (the rwwsb will be set by hardware). to re-enable the rww sect ion, the user software mu st wait until the program- ming is completed (spmen will be clear ed). then, if the rwwsre bit is wr itten to one at the same time as spmen, the next spm instruction within four clock cycles re-enables the rww section. the rww section cannot be re-enabled while the flash is busy with a page erase or a page write (spmen is set). if the rwwsre bit is written while the flash is being l oaded, the flash load o peration will abort and the data l oaded will be lost. ? bit 3 ? blbset: boot lock bit set if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles sets boot lock bits and memory lock bits, according to the data in r0. the data in r1 and the address in the z-pointer are ignored. the blbset bit will au tomatically be cleared upon co mpletion of the lock bit se t, or if no spm instruction is executed within four clock cycles. an lpm instruction within three cycl es after blbset and spmen are set in the spmcsr regist er, will read either the lock bits or the fuse bits (depending on z0 in the z-pointer) into the destination register. see ?reading the fuse and lock bits from software? on page 276 for details. ? bit 2 ? pgwrt: page write if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page write, with the data stored in the temporary buffer. the page address is taken from the high part of the z- pointer. the data in r1 and r0 are ig nored. the pgwrt bit will auto -clear upon completion of a page write, or if no spm instruction is executed within four clock cycles. the cpu is halted during the entire page write operation if the nrww section is addressed. bit 7 6 5 4 3 2 1 0 0x37 (0x57) spmie rwwsb sigrd rwwsre blbset pgwrt pgers spmen spmcsr read/write r/w r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 284 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 ? bit 1 ? pgers: page erase if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page erase. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgers bit will auto-clear upon co mpletion of a page erase, or if no spm in struction is executed within four clock cycles. the cpu is halted during the entire page write operation if the nrw w section is addressed. ? bit 0 ? spmen: store program memory this bit enables the spm instruction for the next four clock cycles. if written to one together with either rwwsre, blbset, pgwrt or pgers, the followi ng spm instruction will have a special meaning, see description above. if only spmen is written, the following spm instruction will store the value in r1:r0 in the temporary page buffer addressed by the z-poin ter. the lsb of the z-pointer is ignored. the spmen bit will au to-clear upon completion of an spm instruction, or if no spm instruction is executed within four clock cycles. during page erase and page write, the spmen bit remains high until the operation is completed. writing any other combination than ?10001?, ?0 1001?, ?00101?, ?00011? or ? 00001? in the lower five bits will have no effect. 285 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 28. memory programming 28.1 program and data memory lock bits the atmega 48a/48pa provides two lock bits and the atmega88a/88pa/168a/168pa/328/328pprovides six lock bits. these can be left unprogrammed (?1?) or can be programmed (?0?) to obtain the additional features listed in table 28-2 . the lock bits can only be erased to ?1? with the chip erase command. the atmega 48a/48pa has no separate boot loader sect ion, and the spm instruction is enabled for the whole flash if the selfprgen fuse is programmed (?0?). otherwise the spm instruction is disabled. notes: 1. ?1? means unprogrammed, ?0? means programmed. 2. only on atmega88a/88pa/168a/168pa/328/328p. notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed table 28-1. lock bit byte (1) lock bit byte bit no description default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) blb12 (2) 5 boot lock bit 1 (unprogrammed) blb11 (2) 4 boot lock bit 1 (unprogrammed) blb02 (2) 3 boot lock bit 1 (unprogrammed) blb01 (2) 2 boot lock bit 1 (unprogrammed) lb2 1 lock bit 1 (unprogrammed) lb1 0 lock bit 1 (unprogrammed) table 28-2. lock bit protection modes (1)(2) memory lock bits protection type lb mode lb2 lb1 1 1 1 no memory lock features enabled. 210 further programming of the flash and eeprom is disabled in parallel and serial programming mode. the fuse bits are locked in both serial and parallel programming mode. (1) 300 further programming and verification of the flash and eeprom is disabled in parallel and serial programming mode. the boot lock bits and fuse bits are locked in both serial and parallel programming mode. (1) 286 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed 28.2 fuse bits the atmega48a/pa/88a/pa/168a/pa/328/p has three fuse bytes. table 28-4 - table 28-9 on page 288 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. note that the fuses are read as logical zero, ?0?, if they are programmed. table 28-3. lock bit protection modes (1)(2) . only atmega88a/88pa/168a/168pa/328/328p. blb0 mode blb02 blb01 111 no restrictions for spm or lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 300 spm is not allowed to write to the application section, and lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 401 lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. blb1 mode blb12 blb11 111 no restrictions for spm or lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to the boot loader section, and lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 401 lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. table 28-4. extended fuse byte for atmega 48a/48pa extended fuse byte bit no description default value ?7? 1 ?6? 1 ?5? 1 ?4? 1 ?3? 1 ?2? 1 ?1? 1 selfprgen 0 self programming enable 1 (unprogrammed) 287 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. the default value of bootsz[1:0] results in maximum boot size. see ?pin name mapping? on page 291 . note: 1. see table 29-17 on page 312 for bodlevel fuse decoding. table 28-5. extended fuse byte for atmega88a/88pa/168a/168pa extended fuse byte bit no description default value ?7? 1 ?6? 1 ?5? 1 ?4? 1 ?3? 1 bootsz1 2 select boot size (see table 27-7 on page 280 and table 27-10 on page 281 for details) 0 (programmed) (1) bootsz0 1 select boot size (see table 27-7 on page 280 and table 27-10 on page 281 for details) 0 (programmed) (1) bootrst 0 select reset vector 1 (unprogrammed) table 28-6. extended fuse byte for atmega328/328p extended fuse byte bit no description default value ?7? 1 ?6? 1 ?5? 1 ?4? 1 ?3? 1 bodlevel2 (1) 2 brown-out detector trigger level 1 (unprogrammed) bodlevel1 (1) 1 brown-out detector trigger level 1 (unprogrammed) bodlevel0 (1) 0 brown-out detector trigger level 1 (unprogrammed) table 28-7. fuse high byte for atmega48a/48pa/88a/88pa/168a/168pa high fuse byte bit no description default value rstdisbl (1) 7 external reset disable 1 (unprogrammed) dwen 6 debugwire enable 1 (unprogrammed) spien (2) 5 enable serial program and data downloading 0 (programmed, spi programming enabled) wdton (3) 4 watchdog timer always on 1 (unprogrammed) eesave 3 eeprom memory is preserved through the chip erase 1 (unprogrammed), eeprom not reserved 288 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 notes: 1. see ?alternate functions of port c? on page 86 for description of rstdisbl fuse. 2. the spien fuse is not accessible in serial programming mode. 3. see ?wdtcsr ? watchdog timer c ontrol register? on page 54 for details. 4. see table 29-17 on page 312 for bodlevel fuse decoding. notes: 1. see ?alternate functions of port c? on page 86 for description of rstdisbl fuse. 2. the spien fuse is not accessible in serial programming mode. 3. see ?wdtcsr ? watchdog timer c ontrol register? on page 54 for details. 4. the default value of bootsz[1:0] results in maximum boot size. see ?pin name mapping? on page 291 . bodlevel2 (4) 2 brown-out detector trigger level 1 (unprogrammed) bodlevel1 (4) 1 brown-out detector trigger level 1 (unprogrammed) bodlevel0 (4) 0 brown-out detector trigger level 1 (unprogrammed) table 28-8. fuse high byte for atmega328/328p high fuse byte bit no description default value rstdisbl (1) 7 external reset disable 1 (unprogrammed) dwen 6 debugwire enable 1 (unprogrammed) spien (2) 5 enable serial program and data downloading 0 (programmed, spi programming enabled) wdton (3) 4 watchdog timer always on 1 (unprogrammed) eesave 3 eeprom memory is preserved through the chip erase 1 (unprogrammed), eeprom not reserved bootsz1 2 select boot size (see table 27-7 on page 280 , table 27-10 on page 281 and table 27-13 on page 282 for details) 0 (programmed) (4) bootsz0 1 select boot size (see table 27-7 on page 280 , table 27-10 on page 281 and table 27-13 on page 282 for details) 0 (programmed) (4) bootrst 0 select reset vector 1 (unprogrammed) table 28-9. fuse low byte low fuse byte bit no description default value ckdiv8 (4) 7 divide clock by 8 0 (programmed) ckout (3) 6 clock output 1 (unprogrammed) sut1 5 select start-up time 1 (unprogrammed) (1) sut0 4 select start-up time 0 (programmed) (1) cksel3 3 select clock source 0 (programmed) (2) table 28-7. fuse high byte for atmega48a/48pa/88a/88pa/168a/168pa (continued) high fuse byte bit no description default value 289 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. the default value of sut1...0 results in maximum start-up time for the default clock source. see table 9-12 on page 32 for details. 2. the default setting of cksel3...0 result s in internal rc oscillator @ 8mhz. see table 9-11 on page 32 for details. 3. the ckout fuse allows the system clock to be output on portb0. see ?clock output buffer? on page 34 for details. 4. see ?system clock prescaler? on page 34 for details. the status of the fuse bits is not affected by chip erase. note that the fuse bits are locked if lock bit1 (lb1) is programmed. program the fuse bits before programming the lock bits. 28.2.1 latching of fuses the fuse values are latched when the device enters pr ogramming mode and changes of the fuse values will have no effect until the part le aves programming mode. this does not apply to the eesave fuse which will take effect once it is programmed. the fuses are also latched on power-up in normal mode. 28.3 signature bytes all atmel microcontrollers have a three-byte signature c ode which identifies the device. this code can be read in both serial and parallel mode, also when the device is locked. the three bytes reside in a separate address space. for the atmega48a/pa/88a/pa/168a/pa/328/p the signature bytes are given in table 28-10 . 28.4 calibration byte the atmega48a/pa/88a/pa/168a/pa/328/p has a byte calibration value for the in ternal rc oscillator. this byte resides in the high byte of address 0x000 in the signatur e address space. during reset, this byte is automatically written into the osccal regist er to ensure correct frequency of the calibrated rc oscillator. cksel2 2 select clock source 0 (programmed) (2) cksel1 1 select clock source 1 (unprogrammed) (2) cksel0 0 select clock source 0 (programmed) (2) table 28-9. fuse low byte (continued) low fuse byte bit no description default value table 28-10. device id part signature bytes address 0x000 0x001 0x002 atmega48a 0x1e 0x92 0x05 atmega48pa 0x1e 0x92 0x0a atmega88a 0x1e 0x93 0x0a atmega88pa 0x1e 0x93 0x0f atmega168a 0x1e 0x94 0x06 atmega168pa 0x1e 0x94 0x0b atmega328 0x1e 0x95 0x14 atmega328p 0x1e 0x95 0x0f 290 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 28.5 page size 28.6 parallel programming paramete rs, pin mapping, and commands this section describes how to parallel program and verify flash program memo ry, eeprom data memory, mem- ory lock bits, and fuse bits in the atmega48a/pa/88a/pa/168a/pa/328/p. pulses are assumed to be at least 250 ns unless otherwise noted. 28.6.1 signal names in this section, some pins of the atmega48a/pa/88a/pa/ 168a/pa/328/p are referenced by signal names describ- ing their functionality during parallel programming, see figure 28-1 and table 28-13 . pins not described in the following table are referenced by pin names. table 28-11. no. of words in a page and no. of pages in the flash device flash size page size pcword no. of pages pcpage pcmsb atmega48a 2k words (4kbytes) 32 words pc[4:0] 64 pc[10:5] 10 at m e g a 4 8 pa 2k words (4kbytes) 32 words pc[4:0] 64 pc[10:5] 10 atmega88a 4k words (8kbytes) 32 words pc[4:0] 128 pc[11:5] 11 at m e g a 8 8 pa 4k words (8kbytes) 32 words pc[4:0] 128 pc[11:5] 11 atmega168a 8k words (16kbytes) 64 words pc[5:0] 128 pc[12:6] 12 atmega168pa 8k words (16kbytes) 64 words pc[5:0] 128 pc[12:6] 12 atmega328 16k words (32kbytes) 64 words pc[5:0] 256 pc[13:6] 13 atmega328p 16k words (32kbytes) 64 words pc[5:0] 256 pc[13:6] 13 table 28-12. no. of words in a page and no. of pages in the eeprom device eeprom size page size pcword no. of pages pcpage eeamsb atmega48a 256bytes 4bytes eea[1:0] 64 eea[7:2] 7 atmega48pa 256bytes 4bytes eea[1:0] 64 eea[7:2] 7 atmega88a 512bytes 4bytes eea[1:0] 128 eea[8:2] 8 atmega88pa 512bytes 4bytes eea[1:0] 128 eea[8:2] 8 atmega168a 512bytes 4bytes eea[1:0] 128 eea[8:2] 8 atmega168pa 512bytes 4bytes eea[1:0] 128 eea[8:2] 8 atmega328 1kbytes 4bytes eea[1:0] 256 eea[9:2] 9 atmega328p 1kbytes 4bytes eea[1:0] 256 eea[9:2] 9 291 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 the xa1/xa0 pins determine the action executed when th e xtal1 pin is given a positive pulse. the bit coding is shown in table 28-15 . when pulsing wr or oe , the command loaded determines the action executed. the different commands are shown in table 28-16 . figure 28-1. parallel programming note: v cc - 0.3v < av cc < v cc + 0.3v, however, av cc should always be within 4.5 - 5.5v table 28-13. pin name mapping signal name in programming mode pin name i/o function rdy/bsy pd1 o 0: device is busy programming, 1: device is ready for new command oe pd2 i output enable (active low) wr pd3 i write pulse (active low) bs1 pd4 i byte select 1 (?0? selects low byte, ?1? selects high byte) xa0 pd5 i xtal action bit 0 xa1 pd6 i xtal action bit 1 pag e l p d 7 i program memory and eeprom data page load bs2 pc2 i byte select 2 (?0? selects low byte, ?1? selects 2?nd high byte) data {pc[1:0]: pb[5:0]} i/o bi-direc tional data bus (output when oe is low) vcc gnd xtal1 pd1 pd2 pd3 pd4 pd5 pd6 pc[1:0]:pb[5:0] data reset pd7 +12 v bs1 xa0 xa1 oe rdy/bsy pagel pc2 wr bs2 avcc +4.5 - 5.5v +4.5 - 5.5v 292 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 28.7 parallel programming 28.7.1 enter programming mode the following algorithm puts the device in parallel (high-voltage) programming mode: 1. set prog_enable pins listed in table 28-14 on page 292 to ?0000?, reset pin to 0v and v cc to 0v. 2. apply 4.5 - 5.5v between v cc and gnd. ensure that v cc reaches at least 1.8v within the next 20 s. 3. wait 20 - 60 s, and apply 11.5 - 12.5v to reset. 4. keep the prog_enable pins unchanged for at least 10s after the high-voltage has been applied to ensure the prog_enable signature has been latched. 5. wait at least 300 s before giving any parallel programming commands. 6. exit programming mode by power the device down or by bringing reset pin to 0v. table 28-14. pin values used to enter programming mode pin symbol value pagel prog_enable[3] 0 xa1 prog_enable[2] 0 xa0 prog_enable[1] 0 bs1 prog_enable[0] 0 table 28-15. xa1 and xa0 coding xa1 xa0 action when xtal1 is pulsed 0 0 load flash or eeprom address (high or low address byte determined by bs1). 0 1 load data (high or low data byte for flash determined by bs1). 1 0 load command 1 1 no action, idle table 28-16. command byte bit coding command byte command executed 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 0001 0001 write eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom 293 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 if the rise time of the v cc is unable to fulfill the requir ements listed above, the follo wing alternative algorithm can be used. 1. set prog_enable pins listed in table 28-14 on page 292 to ?0000?, reset pin to 0v and v cc to 0v. 2. apply 4.5 - 5.5v between v cc and gnd. 3. monitor v cc , and as soon as v cc reaches 0.9 - 1.1v, appl y 11.5 - 12.5v to reset. 4. keep the prog_enable pins unchanged for at least 10s after the high-voltage has been applied to ensure the prog_enable signature has been latched. 5. wait until v cc actually reaches 4.5 -5.5v before giving any parallel programming commands. 6. exit programming mode by power the device down or by bringing reset pin to 0v. 28.7.2 considerations for efficient programming the loaded command and address are retained in the device during programming. for efficient programming, the following should be considered. ? the command needs only be loaded once when writing or reading multiple memory locations. ? skip writing the data val ue 0xff, that is the contents of the en tire eeprom (unless the eesave fuse is programmed) and flash after a chip erase. ? address high byte needs only be loaded before progra mming or reading a new 256 word window in flash or 256 byte eeprom. this consider ation also applies to signature bytes reading. 28.7.3 chip erase the chip erase will erase the flash and eeprom (1) memories plus lock bits. the lock bits are not reset until the program memory has been completely erased. the fuse bits are not changed. a chip erase must be performed before the flas h and/or eeprom are reprogrammed. note: 1. the eeprpom memory is preserved durin g chip erase if the eesave fuse is programmed. load command ?chip erase? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?1000 0000?. this is the command for chip erase. 4. give xtal1 a positive pulse. this loads the command. 5. give wr a negative pulse. this starts the chip erase. rdy/bsy goes low. 6. wait until rdy/bsy goes high before loading a new command. 28.7.4 programming the flash the flash is organized in pages, see table 28-11 on page 290 . when programming the flash, the program data is latched into a page buffer. this allows one page of program data to be programmed simultaneously. the following procedure describes how to program the entire flash memory: a. load command ?write flash? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?0001 0000?. this is the command for write flash. 4. give xtal1 a positive pulse. this loads the command. b. load address low byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?0?. this selects low address. 3. set data = address low byte (0x00 - 0xff). 294 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 4. give xtal1 a positive pulse. this loads the address low byte. c. load data low byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data low byte (0x00 - 0xff). 3. give xtal1 a positive pulse. this loads the data byte. d. load data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?01?. this enables data loading. 3. set data = data high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the data byte. e. latch data 1. set bs1 to ?1?. this selects high data byte. 2. give pagel a positive pulse. this latches the data bytes. (see figure 28-3 for signal waveforms) f. repeat b through e until the entire buffer is filled or until all data within the page is loaded. while the lower bits in the address are mapped to words within the page, the higher bits address the pages within the flash. this is illustrated in figure 28-2 on page 295 . note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a page write. g. load address high byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?1?. this selects high address. 3. set data = address high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address high byte. h. program page 1. give wr a negative pulse. this starts programming of the entire page of data. rdy/bsy goes low. 2. wait until rdy/bsy goes high (see figure 28-3 for signal waveforms). i. repeat b through h until the entire flash is programmed or until all data has been programmed. j. end page programming 1. 1. set xa1, xa0 to ?10?. this enables command loading. 2. set data to ?0000 0000?. this is the command for no operation. 3. give xtal1 a positive pulse. this loads the command, and the internal write signals are reset. 295 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 28-2. addressing the flash which is organized in pages (1) note: 1. pcpage and pcword are listed in table 28-11 on page 290 . figure 28-3. programming the flash waveforms (1) note: 1. ?xx? is don?t care. the letters re fer to the programming description above. 28.7.5 programming the eeprom the eeprom is organized in pages, see table 28-12 on page 290 . when programming the eeprom, the pro- gram data is latched into a page buffer. this allows one page of data to be programmed simultaneously. the programming algorithm for the eeprom data memory is as follows (refer to ?programming the flash? on page 293 for details on command, address and data loading): 1. a: load command ?0001 0001?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. c: load data (0x00 - 0xff). 5. e: latch data (give pagel a positive pulse). k: repeat 3 through 5 until the entire buffer is filled. program memory word address within a page page address within the flash instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter rdy/bsy wr oe reset +12v pagel bs2 0x10 addr. low addr. high data data l ow data h i g h addr. low data low data high xa1 xa0 bs1 xtal1 xx xx xx abcdeb cdegh f 296 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 l: program eeprom page 1. set bs1 to ?0?. 2. give wr a negative pulse. this starts prog ramming of the eeprom page. rdy/bsy goes low. 3. wait until to rdy/bsy goes high before programming the next page (see figure 28-4 for signal waveforms). figure 28-4. programming the eeprom waveforms 28.7.6 reading the flash the algorithm for reading the flash memory is as follows (refer to ?programming the flash? on page 293 for details on command and address loading): 1. a: load command ?0000 0010?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the flash word low byte can now be read at data. 5. set bs1 to ?1?. the flash word high byte can now be read at data. 6. set oe to ?1?. 28.7.7 reading the eeprom the algorithm for reading the eeprom memory is as follows (refer to ?programming the flash? on page 293 for details on command and address loading): 1. a: load command ?0000 0011?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the eeprom data byte can now be read at data. 5. set oe to ?1?. 28.7.8 programming the fuse low bits the algorithm for programming the fuse low bits is as follows (refer to ?programming the flash? on page 293 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. rdy/bsy wr oe reset +12v pagel bs2 0x11 addr. high data addr. low data addr. low data xx xa1 xa0 bs1 xtal1 xx agbceb c el k 297 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 3. give wr a negative pulse and wait for rdy/bsy to go high. 28.7.9 programming the fuse high bits the algorithm for programming the fuse high bits is as follows (refer to ?programming the flash? on page 293 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs1 to ?1? and bs2 to ?0?. this selects high data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs1 to ?0?. this selects low data byte. 28.7.10 programming the extended fuse bits the algorithm for programming the extended fuse bits is as follows (refer to ?programming the flash? on page 293 for details on command and data loading): 1. 1. a: load command ?0100 0000?. 2. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. 3. set bs1 to ?0? and bs2 to ?1?. this selects extended data byte. 4. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. 5. set bs2 to ?0?. this selects low data byte. figure 28-5. programming the fuses waveforms 28.7.11 programming the lock bits the algorithm for programming the lock bits is as follows (refer to ?programming the flash? on page 293 for details on command and data loading): 1. a: load command ?0010 0000?. 2. c: load data low byte. bit n = ?0? programs the lock bit. if lb mode 3 is programmed (lb1 and lb2 is pro- grammed), it is not possible to program the boot lock bits by any external programming mode. 3. give wr a negative pulse and wait for rdy/bsy to go high. rdy/bsy wr oe reset +12v pagel 0x40 data data xx xa1 xa0 bs1 xtal1 ac 0x40 data xx ac write fuse low byte write fuse high byte 0x40 data xx ac write extended fuse byte bs2 298 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 the lock bits can only be cleared by executing chip erase. 28.7.12 reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to ?programming the flash? on page 293 for details on command loading): 1. a: load command ?0000 0100?. 2. set oe to ?0?, bs2 to ?0? and bs1 to ?0?. the status of the fuse low bits can now be read at data (?0? means programmed). 3. set oe to ?0?, bs2 to ?1? and bs1 to ?1?. the status of the fuse high bits can now be read at data (?0? means programmed). 4. set oe to ?0?, bs2 to ?1?, and bs1 to ?0?. the status of the extended fuse bits can now be read at data (?0? means programmed). 5. set oe to ?0?, bs2 to ?0? and bs1 to ?1?. the status of the lock bits can now be read at data (?0? means programmed). 6. set oe to ?1?. figure 28-6. mapping between bs1, bs2 and the fuse and lock bits during read 28.7.13 reading the signature bytes the algorithm for reading the signature bytes is as follows (refer to ?programming the flash? on page 293 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte (0x00 - 0x02). 3. set oe to ?0?, and bs1 to ?0?. the selected signature byte can now be read at data. 4. set oe to ?1?. 28.7.14 reading the calibration byte the algorithm for reading the calibration byte is as follows (refer to ?programming the flash? on page 293 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte, 0x00. 3. set oe to ?0?, and bs1 to ?1?. the calibration byte can now be read at data. 4. set oe to ?1?. lock bits 0 1 bs2 fuse high byte 0 1 bs1 data fuse low byte 0 1 bs2 extended fuse byte 299 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 28.7.15 parallel programming characteristics for characteristics of the parallel programming, see ?parallel programming characteristics? on page 318 . 28.8 serial downloading both the flash and eeprom memory arrays can be programmed using the serial spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and mi so (output) . after reset is set low, the programming enable instruction needs to be executed fi rst before program/erase operations can be executed. note, in table 28-17 on page 299 , the pin mapping for spi programming is listed. not all parts use the spi pins dedicated for the internal spi interface. figure 28-7. serial programming and verify (1) notes: 1. if the device is clocked by the internal oscillator, it is no need to connect a clock source to the xtal1 pin. 2. v cc - 0.3v < av cc < v cc + 0.3v, however, av cc should always be within 1.8 - 5.5v when programming the eeprom, an auto-erase cycle is bu ilt into the self-timed programming operation (in the serial mode only) and there is no need to first execut e the chip erase instruction. the chip erase operation turns the content of ever y memory location in both the progra m and eeprom arrays into 0xff. depending on cksel fuses, a valid cloc k must be present. the minimum low a nd high periods for the serial clock (sck) input are defined as follows: low: > 2 cpu clock cycles for f ck < 12mhz, 3 cpu clock cycles for f ck ? 12mhz high: > 2 cpu clock cycles for f ck < 12mhz, 3 cpu clock cycles for f ck ? 12mhz 28.8.1 serial programming pin mapping 28.8.2 serial programming algorithm when writing serial data to the atmega48a/pa/88a/pa/168a/pa/328/p, data is clocked on the rising edge of sck. vcc gnd xtal1 sck miso mosi reset +1.8 - 5.5v avcc +1.8 - 5.5v (2) table 28-17. pin mapping serial programming symbol pins i/o description mosi pb3 i serial data in miso pb4 o serial data out sck pb5 i serial clock 300 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 when reading data from the atmega48a/pa/88a/pa/ 168a/pa/328/p, data is cloc ked on the falling edge of sck. see figure 28-9 for timing details. to program and verify the atmega48a/pa/88a/pa/168a/pa/328/p in the serial programming mode, the following sequence is recommended (see serial programming instruction set in table 28-19 on page 301 ): 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. in some systems, the program- mer can not guarantee that sck is held low during power-up. in this case, reset must be given a positive pulse of at least two cpu clock cycles duration after sck has been set to ?0?. 2. wait for at least 20ms and enable serial programming by sending the programming enable serial instruction to pin mosi. 3. the serial programming inst ructions will not work if the communicatio n is out of synchronization. when in sync. the second byte (0x53) , will echo back when issuing the third byte of the programming enable instruc- tion. whether the echo is correct or not, all four bytes of the instruction must be transmitted. if the 0x53 did not echo back, give reset a positive pulse and issue a new programming enable command. 4. the flash is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 6 lsb of the address and data together with the load program memory page instruction. to ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. the program memory page is stored by loading the write program memory page instruction with the 7 msb of the address. if polling (rdy/bsy ) is not used, the user must wait at least t wd_flash before issuing the next page (see table 28-18 ). accessing the serial programming interface before the flash write operation completes can result in incorrect programming. 5. a : the eeprom array is programmed one byte at a time by supplying t he address and data together with the appropriate write instruction. an eeprom memory location is firs t automatically erased before new data is written. if polling (rdy/bsy ) is not used, the user must wait at least t wd_eeprom before issuing the next byte (see table 28-18 ). in a chip erased device, no 0xffs in the data file(s) need to be programmed. b : the eeprom array is programmed on e page at a time. the memory page is loaded one byte at a time by supplying the 6 lsb of the addre ss and data together with the load eeprom memory page instruction. the eeprom memory page is stored by loading th e write eeprom memory page instruction with the 7 msb of the address. when usi ng eeprom page access only byte locations loaded with the load eeprom memory page instruction is altered. the remain ing locations remain unchanged. if polling (rdy/bsy ) is not used, the used must wait at least t wd_eeprom before issuing the next byte (see table 28- 18 ). in a chip erased device, no 0xff in the data file(s) need to be programmed. 6. any memory location can be verified by using the read instruction which returns the content at the selected address at serial output miso. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set reset to ?1?. tu r n v cc power off. table 28-18. typical wait delay before writing the next flash or eeprom location symbol minimum wait delay t wd_flash 4.5ms t wd_eeprom 3.6ms t wd_erase 9.0ms 301 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 28.8.3 serial programming instruction set table 28-19 on page 301 and figure 28-8 on page 302 describes the instruction set. notes: 1. not all instructions are applicable for all parts. 2. a = address. 3. bits are programmed ?0?, unprogrammed ?1?. 4. to ensure future compatibility, unused fuses and lock bits should be unprogrammed (?1?) . 5. refer to the corresponding section for fuse and lock bits, calibration and signature bytes and page size. 6. instructions accessing program memory use a word address. this address may be random within the page range. 7. see http://www.atmel.com/avr for application notes regarding programming and programmers. 8. words if the lsb in rdy/bsy data byte out is ?1?, a programming operation is still pending. wait un til this bit returns ?0? before the next instruction is carried out. within the same page, the low data byte must be loaded prior to the high data byte. table 28-19. serial programming instruction set (hexadecimal values) instruction/operation instruction format byte 1 byte 2 byte 3 byte4 programming enable $ac $53 $00 $00 chip erase (program memory/eeprom) $ac $80 $00 $00 poll rdy/bsy $f0 $00 $00 data byte out load instructions load extended address byte (1) $4d $00 extended adr $00 load program memory page, high byte $48 $00 adr lsb high data byte in load program memory page, low byte $40 $00 adr lsb low data byte in load eeprom memory page (page access) $c1 $00 0000 000aa data byte in read instructions read program memory, high byte $28 adr msb adr lsb high data byte out read program memory, low byte $20 adr msb adr lsb low data byte out read eeprom memory $a0 0000 00aa aaaa aaaa data byte out read lock bits $58 $00 $00 data byte out read signature byte $30 $00 0000 000aa data byte out read fuse bits $50 $00 $00 data byte out read fuse high bits $58 $08 $00 data byte out read extended fuse bits $50 $08 $00 data byte out read calibration byte $38 $00 $00 data byte out write instructions (6) write program memory page $4c adr msb (8) adr lsb (8) $00 write eeprom memory $c0 0000 00aa aaaa aaaa data byte in write eeprom memory page (page access) $c2 0000 00aa aaaa aa00 $00 write lock bits $ac $e0 $00 data byte in write fuse bits $ac $a0 $00 data byte in write fuse high bits $ac $a8 $00 data byte in write extended fuse bits $ac $a4 $00 data byte in 302 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 after data is loaded to the page buffer, program the eeprom page, see figure 28-8 on page 302 . figure 28-8. serial programming instruction example 28.8.4 spi serial programming characteristics figure 28-9. serial programming waveforms for characteristics of the spi module see ?spi timing characteristics? on page 313 . byte 1 byte 2 byte 3 byte 4 adr lsb bit 15 b 0 serial programming instruction program memory/ eeprom memory page 0 page 1 page 2 page n-1 page buffer write program memory page/ write eeprom memory page load program memory page (high/low byte)/ load eeprom memory page (page access) byte 1 byte 2 byte 3 byte 4 bit 15 b 0 adr msb page offset page number ad r m ms sb a a adr r l lsb b msb msb lsb lsb serial clock input (sck) serial data input (mosi) (miso) sample serial data output 303 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 29. electrical characteristics ? (t a = -40c to 85c) 29.1 absolute maximum ratings* 29.2 dc characteristics operating temperature.................................. -55 ? c to +125 ? c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c voltage on any pin except reset with respect to ground ................................-0.5v to v cc +0.5v voltage on reset with respect to ground......-0.5v to +13.0v maximum operating voltage ............................................ 6.0v dc current per i/o pin ................................................ 40.0ma dc current v cc and gnd pins................................. 200.0ma table 29-1. common dc characteristics t a = -40 ? c to 105 ? c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. max. units v il input low voltage, except xtal1 and reset pin v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v -0.5 -0.5 0.2v cc (1) 0.3v cc (1) v v ih input high voltage, except xtal1 and reset pins v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v 0.7v cc (2) 0.6v cc (2) v cc + 0.5 v cc + 0.5 v v il1 input low voltage, xtal1 pin v cc = 1.8v - 5.5v -0.5 0.1v cc (1) v v ih1 input high voltage, xtal1 pin v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v 0.8v cc (2) 0.7v cc (2) v cc + 0.5 v cc + 0.5 v v il2 input low voltage, reset pin v cc = 1.8v - 5.5v -0.5 0.1v cc (1) v v ih2 input high voltage, reset pin v cc = 1.8v - 5.5v 0.9v cc (2) v cc + 0.5 v v il3 input low voltage, reset pin as i/o v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v -0.5 -0.5 0.2v cc (1) 0.3v cc (1) v v ih3 input high voltage, reset pin as i/o v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v 0.7v cc (2) 0.6v cc (2) v cc + 0.5 v cc + 0.5 v v ol output low voltage (4) except reset pin i ol = 20ma, v cc = 5v t a =85 ? c0.9 t a =105 ? c1.0 i ol = 10ma, v cc = 3v t a =85 ? c0.6 t a =105 ? c0.7v v oh output high voltage (3) except reset pin i oh = -20ma, v cc = 5v t a =85 ? c4.2 t a =105 ? c4.1 i oh = -10ma, v cc = 3v t a =85 ? c2.3 t a =105 ? c2.1 v 304 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 notes: 1. ?max? means the highest value where the pin is guaranteed to be read as low 2. ?min.? means the lowest value where the pin is guaranteed to be read as high 3. although each i/o port can source more than the test conditions (20ma at v cc = 5v, 10ma at v cc = 3v) under steady state conditions (non-transient), th e following must be observed: atmega48a/pa/88a/pa/168a/pa/328/p: 1] the sum of all i oh , for ports c0 - c5, d0- d4, adc7, reset should not exceed 150ma. 2] the sum of all i oh , for ports b0 - b5, d5 - d7, adc6, xtal1, xtal2 should not exceed 150ma. if ii oh exceeds the test condition, v oh may exceed the related specification. pi ns are not guaranteed to source current greater than the listed test condition. 4. although each i/o port can sink more than the test conditions (20ma at v cc = 5v, 10ma at v cc = 3v) under steady state conditions (non-transient), th e following must be observed: atmega48a/pa/88a/pa/168a/pa/328/p: 1] the sum of all i ol , for ports c0 - c5, adc7, adc6 should not exceed 100ma. 2] the sum of all i ol , for ports b0 - b5, d5 - d7, xtal1, xtal2 should not exceed 100ma. 3] the sum of all i ol , for ports d0 - d4, reset should not exceed 100ma. if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test condition. 29.2.1 atmega48a dc characteristics notes: 1. values with ?minimizing power consumption? enabled (0xff). 2. typical values at 25 ? c. i il input leakage current i/o pin v cc = 5.5v, pin low (absolute value) 1a i ih input leakage current i/o pin v cc = 5.5v, pin high (absolute value) 1a r rst reset pull-up resistor 30 60 k ? r pu i/o pin pull-up resistor 20 50 k ? v acio analog comparator input offset voltage v cc = 5v v in = v cc /2 <10 40 mv i aclk analog comparator input leakage current v cc = 5v v in = v cc /2 -50 50 na t acid analog comparator propagation delay v cc = 2.7v v cc = 4.0v 750 500 ns table 29-2. atmega48a dc characteristics - t a = -40 ? c to 85 ? c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.2 0.55 ma active 4mhz, v cc = 3v 1.2 3.5 ma active 8mhz, v cc = 5v 4.0 12 ma idle 1mhz, v cc = 2v 0.03 0.5 ma idle 4mhz, v cc = 3v 0.21 1.5 ma idle 8mhz, v cc = 5v 0.9 5.5 ma power-save mode (3) 32khz tosc enabled, v cc = 1.8v 0.75 a 32khz tosc enabled, v cc = 3v 0.9 a power-down mode (3) wdt enabled, v cc = 3v 3.9 15 a wdt disabled, v cc = 3v 0.1 2 a table 29-1. common dc characteristics t a = -40 ? c to 105 ? c, v cc = 1.8v to 5.5v (unless otherwise noted) (continued) symbol parameter condition min. typ. max. units 305 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 3. the current consumption values include input leakage current. 29.2.2 atmega48pa dc characteristics ? current consumption notes: 1. values with ?minimizing power consumption? enabled (0xff). 2. typical values at 25 ? c. maximum values are test limits in production. 3. the current consumption values include input leakage current. table 29-3. atmega48pa dc characteristics - t a = -40 ? c to 85 ? c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.2 0.5 ma active 4mhz, v cc = 3v 1.2 2.5 active 8mhz, v cc = 5v 4.0 9 idle 1mhz, v cc = 2v 0.03 0.15 idle 4mhz, v cc = 3v 0.21 0.7 idle 8mhz, v cc = 5v 0.9 2.7 power-save mode (3) 32khz tosc enabled, v cc = 1.8v 0.75 a 32khz tosc enabled, v cc = 3v 0.9 power-down mode (3) wdt enabled, v cc = 3v 3.9 8 wdt disabled, v cc = 3v 0.1 2 table 29-4. atmega48pa dc characteristics - t a = -40 ? c to 105 ? c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.22 0.55 ma active 4mhz, v cc = 3v 1.15 2.65 active 8mhz, v cc = 5v 4.1 9.5 idle 1mhz, v cc = 2v 0.024 0.16 idle 4mhz, v cc = 3v 0.2 0.75 idle 8mhz, v cc = 5v 0.78 2.8 power-save mode (3) 32khz tosc enabled, v cc =1.8v 0.75 a 32khz tosc enabled, v cc = 3v 0.9 power-down mode (3) wdt enabled, v cc = 3v 3.9 10 wdt disabled, v cc = 3v 0.1 5 306 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 29.2.3 atmega88a dc characteristics notes: 1. values with ?minimizing power consumption? enabled (0xff). 2. typical values at 25 ? c. maximum values are test limits in production. 3. the current consumption values include input leakage current. 29.2.4 atmega88pa dc characteristics notes: 1. values with ?minimizing power consumption? enabled (0xff). 2. typical values at 25 ? c. maximum values are test limits in production. 3. the current consumption values include input leakage current. table 29-5. atmega88a dc characteristics - t a = -40 ? c to 85 ? c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.2 0.55 ma active 4mhz, v cc = 3v 1.2 3.5 active 8mhz, v cc = 5v 4.1 12 idle 1mhz, v cc = 2v 0.03 0.5 idle 4mhz, v cc = 3v 0.18 1.5 idle 8mhz, v cc = 5v 0.8 5.5 power-save mode (3) 32khz tosc enabled, v cc = 1.8v 0.8 a 32khz tosc enabled, v cc = 3v 0.9 power-down mode (3) wdt enabled, v cc = 3v 3.9 15 wdt disabled, v cc = 3v 0.1 2 table 29-6. atmega88pa dc characteristics - t a = -40 ? c to 85 ? c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.2 0.5 ma active 4mhz, v cc = 3v 1.2 2.5 active 8mhz, v cc = 5v 4.1 9 idle 1mhz, v cc = 2v 0.03 0.15 idle 4mhz, v cc = 3v 0.18 0.7 idle 8mhz, v cc = 5v 0.8 2.7 power-save mode (3) 32khz tosc enabled, v cc = 1.8v 0.8 a 32khz tosc enabled, v cc = 3v 0.9 power-down mode (3) wdt enabled, v cc = 3v 3.9 8 wdt disabled, v cc = 3v 0.1 2 307 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 notes: 1. values with ?minimizing power consumption? enabled (0xff). 2. typical values at 25 ? c. maximum values are test limits in production. 3. the current consumption values include input leakage current. 29.2.5 atmega168a dc characteristics notes: 1. values with ?minimizing power consumption? enabled (0xff). 2. typical values at 25 ? c. maximum values are test limits in production. 3. the current consumption values include input leakage current. table 29-7. atmega88pa dc characteristics - t a = -40 ? c to 105 ? c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.2 0.6 ma active 4mhz, v cc = 3v 1.2 2.75 active 8mhz, v cc = 5v 4.1 10 idle 1mhz, v cc = 2v 0.03 0.17 idle 4mhz, v cc = 3v 0.18 0.8 idle 8mhz, v cc = 5v 0.8 3 power-save mode (3) 32khz tosc enabled, v cc = 1.8v 0.8 a 32khz tosc enabled, v cc = 3v 0.9 power-down mode (3) wdt enabled, v cc = 3v 3.9 10 wdt disabled, v cc = 3v 0.1 5 table 29-8. atmega168a dc characteristics - t a = -40 ? c to 85 ? c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.2 0.55 ma active 4mhz, v cc = 3v 1.2 3.5 active 8mhz, v cc = 5v 4.2 12 idle 1mhz, v cc = 2v 0.03 0.5 idle 4mhz, v cc = 3v 0.2 1.5 idle 8mhz, v cc = 5v 0.9 5.5 power-save mode (3) 32khz tosc enabled, v cc = 1.8v 0.75 a 32khz tosc enabled, v cc = 3v 0.83 power-down mode (3) wdt enabled, v cc = 3v 4.1 15 wdt disabled, v cc = 3v 0.1 2 308 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 29.2.6 atmega168pa dc characteristics notes: 1. values with ?minimizing power consumption? enabled (0xff). 2. typical values at 25 ? c. maximum values are test limits in production. 3. the current consumption values include input leakage current. notes: 1. values with ?minimizing power consumption? enabled (0xff). 2. typical values at 25 ? c. maximum values are test limits in production. 3. the current consumption values include input leakage current. table 29-9. atmega168pa dc characteristics - t a = -40 ? c to 85 ? c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.2 0.5 ma active 4mhz, v cc = 3v 1.2 2.5 active 8mhz, v cc = 5v 4.2 9 idle 1mhz, v cc = 2v 0.03 0.15 idle 4mhz, v cc = 3v 0.2 0.7 idle 8mhz, v cc = 5v 0.9 2.7 power-save mode (3) 32khz tosc enabled, v cc = 1.8v 0.75 a 32khz tosc enabled, v cc = 3v 0.83 power-down mode (3) wdt enabled, v cc = 3v 4.1 8 wdt disabled, v cc = 3v 0.1 2 table 29-10. atmega168pa dc characteristics - t a = -40 ? c to 105 ? c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.3 0.6 ma active 4mhz, v cc = 3v 1.8 2.75 active 8mhz, v cc = 5v 6.7 10 idle 1mhz, v cc = 2v 0.06 0.2 idle 4mhz, v cc = 3v 0.4 0.8 idle 8mhz, v cc = 5v 1.7 3 power-save mode (3) 32khz tosc enabled, v cc = 1.8v 0.8 a 32khz tosc enabled, v cc = 3v 0.9 power-down mode (3) wdt enabled, v cc = 3v 4.6 10 wdt disabled, v cc = 3v 0.1 5 309 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 29.2.7 atmega328 dc characteristics notes: 1. values with ?minimizing power consumption? enabled (0xff). 2. typical values at 25 ? c. maximum values are test limits in production. 3. the current consumption values include input leakage current. 29.2.8 atmega328p dc characteristics notes: 1. values with ?minimizing power consumption? enabled (0xff). 2. typical values at 25 ? c. maximum values are test limits in production. 3. the current consumption values include input leakage current. table 29-11. atmega328 dc characteristics - t a = -40 ? c to 85 ? c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.3 0.55 ma active 4mhz, v cc = 3v 1.7 3.5 active 8mhz, v cc = 5v 5.2 12 idle 1mhz, v cc = 2v 0.04 0.5 idle 4mhz, v cc = 3v 0.3 1.5 idle 8mhz, v cc = 5v 1.2 5.5 power-save mode (3) 32khz tosc enabled, v cc = 1.8v 0.8 a 32khz tosc enabled, v cc = 3v 0.9 power-down mode (3) wdt enabled, v cc = 3v 4.2 15 wdt disabled, v cc = 3v 0.1 2 table 29-12. atmega328p dc characteristics - t a = -40 ? c to 85 ? c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.3 0.5 ma active 4mhz, v cc = 3v 1.7 2.5 active 8mhz, v cc = 5v 5.2 9 idle 1mhz, v cc = 2v 0.04 0.15 idle 4mhz, v cc = 3v 0.3 0.7 idle 8mhz, v cc = 5v 1.2 2.7 power-save mode (3) 32khz tosc enabled, v cc = 1.8v 0.8 a 32khz tosc enabled, v cc = 3v 0.9 power-down mode (3) wdt enabled, v cc = 3v 4.2 8 wdt disabled, v cc = 3v 0.1 2 310 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 notes: 1. values with ?minimizing power consumption? enabled (0xff). 2. typical values at 25 ? c. maximum values are test limits in production. 3. the current consumption values include input leakage current. 29.3 speed grades maximum frequency is dependent on v cc. as shown in figure 29-1 , the maximum frequency vs. v cc curve is lin- ear between 1.8v < v cc < 2.7v and between 2.7v < v cc < 4.5v. figure 29-1. maximum frequency vs. v cc table 29-13. atmega328p dc characteristics - t a = -40 ? c to 105 ? c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.3 0.5 ma active 4mhz, v cc = 3v 1.7 2.5 active 8mhz, v cc = 5v 5.2 9.0 idle 1mhz, v cc = 2v 0.04 0.15 idle 4mhz, v cc = 3v 0.3 0.7 idle 8mhz, v cc = 5v 1.2 2.7 power-save mode (3) 32khz tosc enabled, v cc = 1.8v 0.8 a 32khz tosc enabled, v cc = 3v 0.9 power-down mode (3) wdt enabled, v cc = 3v 4.2 10 wdt disabled, v cc = 3v 0.1 5 4 mhz 1. 8 v 2.7v 4.5v 10 mhz 20 mhz 5.5v sa fe oper a ting are a 311 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 29.4 clock characteristics 29.4.1 calibrated internal rc oscillator accuracy 29.4.2 external clock drive waveforms figure 29-2. external clock drive waveforms 29.4.3 external clock drive table 29-14. calibration accuracy of internal rc oscillator frequency v cc temperature calibration accuracy factory calibration 8.0mhz 3v 25 ? c10% user calibration 7.3 - 8.1mhz 1.8v - 5.5v -40 ? c - 85 ? c1% v il1 v ih1 table 29-15. external clock drive symbol parameter v cc = 1.8 - 5.5v v cc = 2.7 - 5.5v v cc = 4.5 - 5.5v units min. max. min. max. min. max. 1/t clcl oscillator frequency 0 4 0 10 0 20 mhz t clcl clock period 250 100 50 ns t chcx high time 100 40 20 ns t clcx low time 100 40 20 ns t clch rise time 2.0 1.6 0.5 ? s t chcl fall time 2.0 1.6 0.5 ? s ? t clcl change in period from one clock cycle to the next 22 2% 312 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 29.5 system and reset characteristics notes: 1. values are guidelines only. 2. the power-on reset will not work unless the supply voltage has been below v pot (falling) notes: 1. v bot may be below nominal minimum operating voltage for some devices. for devices where this is the case, the device is tested down to v cc = v bot during the production test. this guarantees that a brown-out reset will occur before v cc drops to a voltage where correct operation of the microcontroller is no longer guaran teed. the test is performed using bodlevel = 110, 101 and 100. 2. v bot tested at 25 ? c and 85 ? c in production table 29-16. reset, brown-out and internal voltage characteristics (1) symbol parameter min. typ max units v pot power-on reset threshold voltage (rising) 1.1 1.4 1.6 v power-on reset threshold voltage (falling) (2) 0.6 1.3 1.6 v sr on power-on slope rate 0.01 10 v/ms v rst reset pin threshold voltage 0.2 v cc 0.9 v cc v t rst minimum pulse width on reset pin 2.5 s v hyst brown-out detector hysteresis 50 mv t bod min. pulse width on brown-out reset 2 s v bg bandgap reference voltage v cc =2.7 t a =25c 1.0 1.1 1.2 v t bg bandgap reference start-up time v cc =2.7 t a =25c 40 70 s i bg bandgap reference current consumption v cc =2.7 t a =25c 10 a table 29-17. bodlevel fuse coding (1) (2) bodlevel 2:0 fuses min. v bot typ v bot max v bot units 111 bod disabled 110 1.7 1.8 2.0 v 101 2.5 2.7 2.9 100 4.1 4.3 4.5 011 reserved 010 001 000 313 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 29.6 spi timing characteristics see figure 29-3 and figure 29-4 for details. note: 1. in spi programming mode the minimum sck high/low period is: - 2 t clcl for f ck < 12mhz - 3 t clcl for f ck > 12mhz figure 29-3. spi interface timing requirements (master mode) table 29-18. spi timing parameters description mode min. typ max 1 sck period master see table 19-5 ns 2 sck high/low master 50% duty cycle 3 rise/fall time master 3.6 4 setup master 10 5hold master 10 6 out to sck master 0.5 ? t sck 7 sck to out master 10 8 sck to out high master 10 9ss low to out slave 15 10 sck period slave 4 ? t ck 11 sck high/low (1) slave 2 ? t ck 12 rise/fall time slave 1600 13 setup slave 10 14 hold slave t ck 15 sck to out slave 15 16 sck to ss high slave 20 17 ss high to tri-state slave 10 18 ss low to sck slave 20 mo si (data output) sck (cpol = 1) mi so (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 61 22 3 45 8 7 314 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 29-4. spi interface timing requirements (slave mode) mi so (data output) sck (cpol = 1) mo si (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 10 11 11 12 13 14 17 15 9 x 16 315 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 29.7 two-wire serial in terface characteristics table 29-19 describes the requirements for devices connected to the 2-wire serial bus. the atmega48a/pa/88a/pa/168a/pa/328/p 2-wire serial interface meets or exceeds these requirements under the noted conditions. timing symbols refer to figure 29-5 . notes: 1. in atmega48a/pa/88a/pa/168a/pa/328/p, th is parameter is characterized and not 100% tested. 2. required only for f scl > 100khz. table 29-19. two-wire serial bus requirements symbol parameter condition min. max units v il input low-voltage -0.5 0.3 v cc v v ih input high-voltage 0.7 v cc v cc + 0.5 v v hys (1) hysteresis of schmitt trigger inputs 0.05 v cc (2) ?v v ol (1) output low-voltage 3ma sink current 0 0.4 v t r (1) rise time for both sda and scl 20 + 0.1c b (3)(2) 300 ns t of (1) output fall time from v ihmin to v ilmax 10pf < c b < 400pf (3) 20 + 0.1c b (3)(2) 250 ns t sp (1) spikes suppressed by input filter 0 50 (2) ns i i input current each i/o pin 0.1v cc < v i < 0.9v cc -10 10 a c i (1) capacitance for each i/o pin ? 10 pf f scl scl clock frequency f ck (4) > max(16f scl , 250khz) (5) 0 400 khz rp value of pull-up resistor f scl ? 100khz f scl > 100khz t hd;sta hold time (repeated) start condition f scl ? 100khz 4.0 ? s f scl > 100khz 0.6 ? s t low low period of the scl clock f scl ? 100khz 4.7 ? s f scl > 100khz 1.3 ? s t high high period of the scl clock f scl ? 100khz 4.0 ? s f scl > 100khz 0.6 ? s t su;sta set-up time for a repeated start condition f scl ? 100khz 4.7 ? s f scl > 100khz 0.6 ? s t hd;dat data hold time f scl ? 100khz 0 3.45 s f scl > 100khz 0 0.9 s t su;dat data setup time f scl ? 100khz 250 ? ns f scl > 100khz 100 ? ns t su;sto setup time for stop condition f scl ? 100khz 4.0 ? s f scl > 100khz 0.6 ? s t buf bus free time between a stop and start condition f scl ? 100khz 4.7 ? s f scl > 100khz 1.3 ? s v cc 0,4v ? 3ma --------------------------- - 1000ns c b ---------------- - ? v cc 0,4v ? 3ma --------------------------- - 300ns c b ------------- - ? 316 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 3. c b = capacitance of one bus line in pf. 4. f ck = cpu clock frequency 5. this requirement applies to all atmega48a/pa/88a/pa/168a/pa/ 328/p 2-wire serial interface operation. other devices con- nected to the 2-wire serial bus need only obey the general f scl requirement. figure 29-5. two-wire serial bus timing t su;sta t low t high t low t of t hd;sta t hd;dat t su;dat t su;sto t buf scl sda t r 317 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 29.8 adc characteristics note: 1. av cc absolute min./max: 1.8v/5.5v table 29-20. adc characteristics symbol parameter condition min. typ max units resolution 10 bits absolute accu racy (including inl, dnl, quantization error, gain and offset error) v ref = 4v, v cc = 4v, adc clock = 200khz 2lsb v ref = 4v, v cc = 4v, adc clock = 1mhz 4.5 lsb v ref = 4v, v cc = 4v, adc clock = 200khz noise reduction mode 2lsb v ref = 4v, v cc = 4v, adc clock = 1mhz noise reduction mode 4.5 lsb integral non-linearity (inl) v ref = 4v, v cc = 4v, adc clock = 200khz 0.5 lsb differential non-linearity (dnl) v ref = 4v, v cc = 4v, adc clock = 200khz 0.25 lsb gain error v ref = 4v, v cc = 4v, adc clock = 200khz 2lsb offset error v ref = 4v, v cc = 4v, adc clock = 200khz 2lsb conversion time free running conversion 13 260 s clock frequency 50 1000 khz av cc (1) analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage 1.0 av cc v v in input voltage gnd v ref v input bandwidth 38.5 khz v int internal voltage reference 1.0 1.1 1.2 v r ref reference input resistance 32 k ? r ain analog input resistance 100 m ? 318 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 29.9 parallel programmi ng characteristics notes: 1. t wlrh is valid for the write flash, write eeprom, wr ite fuse bits and write lock bits commands. 2. t wlrh_ce is valid for the chip erase command. table 29-21. parallel programming characteristics, v cc = 5v 10% symbol parameter min. typ max units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250 ? a t dvxh data and control valid before xtal1 high 67 ns t xlxh xtal1 low to xtal1 high 200 ns t xhxl xtal1 pulse width high 150 ns t xldx data and control hold after xtal1 low 67 ns t xlwl xtal1 low to wr low 0 ns t xlph xtal1 low to pagel high 0 ns t plxh pagel low to xtal1 high 150 ns t bvph bs1 valid before pagel high 67 ns t phpl pagel pulse width high 150 ns t plbx bs1 hold after pagel low 67 ns t wlbx bs2/1 hold after wr low 67 ns t plwl pagel low to wr low 67 ns t bvwl bs1 valid to wr low 67 ns t wlwh wr pulse width low 150 ns t wlrl wr low to rdy/bsy low 0 1 ? s t wlrh wr low to rdy/bsy high (1) 3.7 4.5 ms t wlrh_ce wr low to rdy/bsy high for chip erase (2) 7.5 9 ms t xlol xtal1 low to oe low 0 ns t bvdv bs1 valid to data valid 0 250 ns t oldv oe low to data valid 250 ns t ohdz oe high to data tri-stated 250 ns 319 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 29-6. parallel programming timing, including some general timing requirements figure 29-7. parallel programming timing, loading sequence with timing requirements (1) note: 1. the timing requirements shown in figure 29-6 (i.e., t dvxh , t xhxl , and t xldx ) also apply to loading operation. figure 29-8. parallel programming timing, reading sequence (within the same page) with timing requirements (1) note: 1. the timing requirements shown in figure 29-6 (i.e., t dvxh , t xhxl , and t xldx ) also apply to reading operation. data & contol (data, xa0/1, bs1, bs2) xtal1 t xhxl t wlwh t dvxh t xldx t plwl t wlrh wr rdy/bsy pagel t phpl t plbx t bvph t xlwl t wlbx t bvwl wlrl xtal1 pagel t plxh xlxh t t xlph addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) load data (low byte) load data (high byte) load data load address (low byte) xtal1 oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) read data (low byte) read data (high byte) load address (low byte) t bvdv t oldv t xlol t ohdz 320 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 30. electrical characteristics (t a = -40c to 105c) 30.1 absolute maximum ratings* 30.2 dc characteristics operating temperature . . . . . . . . . . . -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect device reliability. storage temperature . . . . . . . . . . . . . -65c to +150c voltage on any pin except reset with respect to ground. . . . . . . . . . -0.5v to v cc +0.5v voltage on reset with respect to ground-0.5v to +13.0v maximum operating voltage . . . . . . . . . . . . . . . . 6.0v dc current per i/o pin. . . . . . . . . . . . . . . . . . . 40.0ma dc current v cc and gnd pins . . . . . . . . . . . 200.0ma symbol parameter condition min. typ. max. units v il input low voltage, except xtal1 and reset pin v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v -0.5 -0.5 0.2v cc (1) 0.3v cc (1) v v ih input high voltage, except xtal1 and reset pins v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v 0.7v cc (2) 0.6v cc (2) v cc + 0.5 v cc + 0.5 v il1 input low voltage, xtal1 pin v cc = 1.8v - 5.5v -0.5 0.1v cc (1) v ih1 input high voltage, xtal1 pin v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v 0.8v cc (2) 0.7v cc (2) v cc + 0.5 v cc + 0.5 v il2 input low voltage, reset pin v cc = 1.8v - 5.5v -0.5 0.1v cc (1) v ih2 input high voltage, reset pin v cc = 1.8v - 5.5v 0.9v cc (2) v cc + 0.5 v il3 input low voltage, reset pin as i/o v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v -0.5 -0.5 0.2v cc (1) 0.3v cc (1) v ih3 input high voltage, reset pin as i/o v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v 0.7v cc (2) 0.6v cc (2) v cc + 0.5 v cc + 0.5 v ol output low voltage (4) except reset pin i ol = 20ma, v cc = 5v i ol = 10ma, v cc = 3v 0.9 0.6 v oh output high voltage (4) except reset pin i oh = -20ma, v cc = 5v i oh = -10ma, v cc = 3v 4.2 2.3 321 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 notes: 1. ?max? means the highest value wher e the pin is guaranteed to be read as low 2. ?min.? means the lowest value where the pin is guaranteed to be read as high 3. although each i/o port can sink more than the test conditions (20ma at v cc = 5v, 10ma at v cc = 3v) under steady state conditions (non-transient), the following must be observed: atmega168p: 1] the sum of all i ol , for ports c0 - c5, adc7, adc6 should not exceed 100ma 2] the sum of all i ol , for ports b0 - b5, d5 - d7, xtal1, xtal2 should not exceed 100ma 3] the sum of all i ol , for ports d0 - d4, reset should not exceed 100ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaran teed to sink current greater than the listed test condition 4. although each i/o port can source more than the test conditions (20ma at v cc = 5v, 10ma at v cc = 3v) under steady state conditions (non-transient), the fol- lowing must be observed: atmega168p: 1] the sum of all i oh , for ports c0 - c5, d0- d4, adc7, reset should not exceed 150ma 2] the sum of all i oh , for ports b0 - b5, d5 - d7, adc6, xtal1, xtal2 should not exceed 150ma if ii oh exceeds the test condition, v oh may exceed the related specification. pins are not guarant eed to source current greater than the listed test condition 30.2.1 atmega48pa dc characteristics ? current consumption notes: 1. values with ?minimizing power consumption? enabled (0xff) 2. typical values at 25c. maximum values are test limits in production 3. the current consumption values include input leakage current i il input leakage current i/o pin v cc = 5.5v, pin low (absolute value) 1 a i ih input leakage current i/o pin v cc = 5.5v, pin high (absolute value) 1 r rst reset pull-up resistor 30 60 k ? r pu i/o pin pull-up resistor 20 50 v acio analog comparator input offset voltage v cc = 5v v in = v cc /2 <10 40 mv i aclk analog comparator input leakage current v cc = 5v v in = v cc /2 -50 50 na t acid analog comparator propagation delay v cc = 2.7v v cc = 4.0v 750 500 ns symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.22 0.55 ma active 4mhz, v cc = 3v 1.15 2.65 active 8mhz, v cc = 5v 4.1 9.5 idle 1mhz, v cc = 2v 0.024 0.16 idle 4mhz, v cc = 3v 0.2 0.75 idle 8mhz, v cc = 5v 0.78 2.8 power-save mode (3) 32khz tosc enabled, v cc =1.8v a 32khz tosc enabled, v cc = 3v power-down mode (3) wdt enabled, v cc = 3v 3.9 8.5 wdt disabled, v cc = 3v 0.1 3 symbol parameter condition min. typ. max. units 322 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 30.2.2 atmega88pa dc characteristics ? current consumption notes: 1. values with ?minimizing power consumption? enabled (0xff) 2. typical values at 25c. maximum values are test limits in production 3. the current consumption values include input leakage current 30.2.3 atmega168p dc characteristics ? current consumption notes: 1. values with ?minimizing power consumption? enabled (0xff) 2. typical values at 25 ? c. maximum values are test limits in production 3. the current consumption values include input leakage current 4. maximum values are characterized val ues and not test limits in production symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.2 0.6 ma active 4mhz, v cc = 3v 1.2 2.75 active 8mhz, v cc = 5v 4.1 10 idle 1mhz, v cc = 2v 0.03 0.17 idle 4mhz, v cc = 3v 0.18 0.8 idle 8mhz, v cc = 5v 0.8 3 power-save mode (3) 32khz tosc enabled, v cc =1.8v 0.8 a 32khz tosc enabled, v cc = 3v 0.9 power-down mode (3) wdt enabled, v cc = 3v 3.9 8.8 wdt disabled, v cc = 3v 0.1 4 symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.3 0.6 ma active 4mhz, v cc = 3v 1.8 2.75 active 8mhz, v cc = 5v 6.7 10 idle 1mhz, v cc = 2v 0.06 0.2 idle 4mhz, v cc = 3v 0.4 0.8 idle 8mhz, v cc = 5v 1.7 3 power-save mode (3)(4) 32khz tosc enabled, v cc = 1.8v 0.8 2.2 a 32khz tosc enabled, v cc = 3v 0.9 2.9 power-down mode (3) wdt enabled, v cc = 3v 4.6 8.8 wdt disabled, v cc = 3v 0.1 2.2 323 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 30.2.4 atmega328p dc characteristics ? current consumption notes: 1. values with ?minimizing power consumption? enabled (0xff) 2. typical values at 25 ? c. maximum values are test limits in production 3. the current consumption values include input leakage current 4. maximum values are characterized val ues and not test limits in production symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.3 0.5 ma active 4mhz, v cc = 3v 1.7 2.5 active 8mhz, v cc = 5v 5.2 9.0 idle 1mhz, v cc = 2v 0.04 0.15 idle 4mhz, v cc = 3v 0.3 0.7 idle 8mhz, v cc = 5v 1.2 2.7 power-save mode (3)(4) 32khz tosc enabled, v cc = 1.8v 0.8 1.6 a 32khz tosc enabled, v cc = 3v 0.9 2.6 power-down mode (3) wdt enabled, v cc = 3v 4.2 8.0 wdt disabled, v cc = 3v 0.1 2.0 324 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31. typical characteristics ? (t a = -40c to 85c) the following charts show typical behavior. these figures are not tested during manufacturing. all current con- sumption measurements are performed with all i/o pins conf igured as inputs and with internal pull-ups enabled. a square wave generator with rail-to-rail output is used as clock source. all active- and idle current consumption measurements are done with all bits in the prr register set and thus, the corresponding i/o modules are turned off. also the a nalog comparator is disabled during these measurements. the ?atmega88pa: supply current of io modules? on page 405 and page 455 shows the additional current con- sumption compared to i cc active and i cc idle for every i/o module controlled by the power reduction register. see ?power reduction register? on page 41 for details. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors such as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient temperature. the dominating factors are operating voltage and frequency. the current drawn from capacitive loaded pins may be estimated (for one pin) as c l * v cc *f where c l = load capac- itance, v cc = operating voltage and f = average switching frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. the difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the di fferential current drawn by the watchdog timer. 325 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.1 atmega48a typical characteristics 31.1.1 active supply current figure 31-1. atmega48a: active supply current vs. low frequency (0.1-1.0mhz) figure 31-2. atmega48a: active supply current vs. frequency (1-20mhz 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.2 0.4 0.6 0. 8 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 2 4 6 8 10 12 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8v 2.7 v 3.3 v 4.0 v 326 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-3. atmega48a: active supply current vs. v cc (internal rc oscillator, 128khz) figure 31-4. atmega48a: active supply current vs. v cc (internal rc oscillator, 1mhz) 8 5 c 25 c -40 c 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 327 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-5. atmega48a: active supply current vs. v cc (internal rc oscillator, 8mhz) 31.1.2 idle supply current figure 31-6. atmega48a: idle supply current vs. low frequency (0.1-1.0mhz) 8 5 c 25 c -40 c 0 1 2 3 4 5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 328 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-7. atmega48a: idle supply current vs. frequency (1-20mhz) figure 31-8. atmega48a: idle supply current vs. v cc (internal rc oscillator, 128khz) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 3 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 3.3 v 4.0 v 8 5 c 25 c -40 c 0 0.007 0.014 0.021 0.02 8 0.035 0.042 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 329 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-9. atmega48a: idle supply current vs. v cc (internal rc oscillator, 1mhz) figure 31-10. atmega48a: idle supply current vs. vcc (internal rc oscillator, 8mhz) 8 5 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 330 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.1.3 atmega48a: supply current of io modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules are controlled by the power reduc- tion register. see ?power reduction register? on page 41 for details. it is possible to calculate the typical cu rrent consumption based on the numbers from table 31-2 on page 330 for other v cc and frequency settings than listed in table 31-1 on page 330 . 31.1.3.1 example calculate the expected current consumption in idle mode with timer1, adc, and spi enabled at v cc = 2.0v and f = 1mhz. from table 31-4 on page 355 , third column, we see that we need to add 11.2% for the timer1, 22.1% for the adc, and 17.6% for the spi module. reading from figure 31-53 on page 352 , we find that the idle current consumption is ~0.028 ma at v cc = 2.0v and f = 1mhz. the total current consumption in idle mode with timer1, adc, and spi enabled, gives: table 31-1. atmega48pa: additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz prusart0 2.9ua 20.7a 97.4a prtwi 6.0a 44.8a 219.7a prtim2 5.0a 34.5a 141.3aa prtim1 3.6a 24.4a 107.7a prtim0 1.4a 9.5a 38.4a prspi 5.0a 38.0a 190.4a pradc 6.1a 47.4a 244.7a table 31-2. atmega48pa: additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 31-48 on page 350 and figure 31-49 on page 350 ) additional current consumption compared to idle with external clock (see figure 31-53 on page 352 and figure 31-54 on page 353 ) prusart0 1.8% 11.4% prtwi 3.9% 20.6% prtim2 2.9% 15.7% prtim1 2.1% 11.2% prtim0 0.8% 4.2% prspi 3.3% 17.6% pradc 4.2% 22.1% i cc total 0.028 ma (1 + 0.112 + 0.221 + 0.176) ? 0.042 ma ?? 331 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.1.4 power-down supply current figure 31-11. atmega48a: power-down supply current vs. v cc (watchdog timer disabled) figure 31-12. atmega48a: power-down supply current vs. v cc (watchdog timer enabled) 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -40 c 0 2 4 6 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 332 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.1.5 power-save supply current figure 31-13. atmega48a: power-save supply current vs. v cc (watchdog timer disabled and 32khz crystal oscillator running) 31.1.6 standby supply current figure 31-14. atmega48a: standby supply current vs. vcc (watchdog timer disabled w atchdog timer disabled and 32 khz crystal oscillator ru nn i n g 8 5 c 25 c -40 c 0 0.4 0. 8 1.2 1.6 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 450khz_res 2mhz_xtal 2mhz_res 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 333 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.1.7 pin pull-up figure 31-15. atmega48a: i/o pin pull-up resistor current vs. input voltage (v cc = 1.8 v) figure 31-16. atmega48a: i/o pin pull-up resistor current vs. input voltage (v cc = 2.7 v) 8 5 c 25 c -40 c 0 10 20 30 40 50 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v op ( v ) i op ( u a) 8 5 c 25 c -40 c 0 10 20 30 40 50 60 70 0 0.5 1 1.5 2 2.5 3 v op ( v ) i op ( u a) 334 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-17. atmega48a: i/o pin pull-up resistor current vs. input voltage (v cc = 5v) figure 31-18. atmega48a: reset pull-up resistor current vs. reset pin voltage (v cc = 1.8v)) 8 5 c 25 c -40 c 0 20 40 60 8 0 100 120 140 012345 v op ( v ) i op ( u a) 8 5 c 25 c -40 c 0 5 10 15 20 25 30 35 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v reset ( v ) i reset ( u a) 335 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-19. atmega48a: reset pull-up resistor current vs. reset pin voltage (v cc = 2.7 v) figure 31-20. atmega48a: reset pull-up resistor current vs. reset pin voltage (v cc = 5v) 8 5 c 25 c -40 c 0 10 20 30 40 50 60 0 0.5 1 1.5 2 2.5 3 v reset ( v ) i reset ( u a) 8 5 c 25 c -40 c 0 20 40 60 8 0 100 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v reset ( v ) i reset ( u a) 336 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.1.8 pin driver strength figure 31-21. atmega48a: i/o pin output voltage vs. sink current (v cc = 3 v) figure 31-22. atmega48a: i/o pin output voltage vs. sink current (v cc = 5 v) 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 04 8 12 16 20 i ol (ma) v ol ( v ) 8 5 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 04 8 12 16 20 i ol (ma) v ol ( v ) 337 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-23. atmega48a: i/o pin output voltage vs. source current (vcc = 3 v) figure 31-24. atmega48a: i/o pin output voltage vs. source current (v cc = 5 v) 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 3.5 04 8 12 16 20 i oh (ma) v oh ( v ) 8 5 c 25 c -40 c 4.2 4.3 4.4 4.5 4.6 4.7 4. 8 4.9 5 04 8 12 16 20 i oh (ma) v oh ( v ) 338 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.1.9 pin threshold and hysteresis figure 31-25. atmega48a: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 31-26. atmega48a: i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0?) 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 339 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-27. atmega48a: i/o pin input hysteresis vs. v cc figure 31-28. atmega48a: reset input threshold voltage vs. v cc (v ih , i/o pin read as ?1)? 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (v) 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 340 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-29. )atmega48a: reset input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 31-30. atmega48a: reset pin input hysteresis vs. v cc 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (v) 341 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.1.10 bod threshold figure 31-31. atmega48a: bod thresholds vs. te mperature (bodlevel is 1.8 v) figure 31-32. atmega48a: bod thresholds vs. te mperature (bodlevel is 2.7 v) rising v cc falling v cc 1.79 1. 8 1. 8 1 1. 8 2 1. 8 3 1. 8 4 1. 8 5 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re (c) threshold ( v ) rising v cc falling v cc 2.62 2.64 2.66 2.6 8 2.7 2.72 2.74 2.76 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re (c) threshold ( v ) 342 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-33. atmega48a: bod thresholds vs. te mperature (bodlevel is 4.3 v) figure 31-34. atmega48a: bandgap voltage vs. v cc rising v cc falling v cc 4.24 4.26 4.2 8 4.3 4.32 4.34 4.36 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re (c) threshold ( v ) 8 5 c 25 c -40 c 1.09 1.092 1.094 1.096 1.09 8 1.1 1.102 1.104 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) bandgap v oltage ( v ) 343 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.1.11 internal oscillator speed figure 31-35. atmega48a: watchdog oscillator frequen cy vs. temperature figure 31-36. atmega48a: watchdog os cillator frequency vs. v cc 5.5 v 4.0 v 3.3 v 2.7 v 104 106 10 8 110 112 114 116 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re (c) f rc (khz) 8 5 c 25 c -40 c 106 10 8 110 112 114 116 11 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) f rc (khz) 344 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-37. atmega48a: calibrated 8mhz rc oscillator frequency vs. v cc figure 31-38. atmega48a: calibrated 8mhz rc osc illator frequency vs. temperature 8 5 c 25 c -40 c 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) f rc (mhz) 5.5 v 3.3 v 1. 8 v 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re (c) f rc (mhz) 345 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-39. atmega48a: calibrated 8mhz rc osc illator frequency vs. osccal value 31.1.12 current consumption of peripheral units figure 31-40. atmega48a: adc current vs. v cc (aref = av cc ) 8 5 c 25 c -40 c 0 2 4 6 8 10 12 14 16 016324 8 64 8 0 96 112 12 8 144 160 176 192 20 8 224 240 256 osccal (x1) f rc (mhz) 8 5 c 25 c -40 c 0 50 100 150 200 250 300 350 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 346 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-41. atmega48a: analog comparator current vs. v cc figure 31-42. atmega48a: aref external reference current vs. v cc 8 5 c 25 c -40 c 0 10 20 30 40 50 60 70 8 0 90 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -40 c 0 20 40 60 8 0 100 120 140 160 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 347 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-43. atmega48a brownout detector current vs. v cc figure 31-44. atmega48a: programming current vs. v cc 8 5 c 25 c -40 c 0 8 16 24 32 40 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -40 c 0 1 2 3 4 5 6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 348 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.1.13 current consumption in reset and reset pulsewidth figure 31-45. atmega48a: reset supply current vs. low frequency (0.1 - 1.0mhz) figure 31-46. atmega48a: reset supply current vs. frequency (1 - 20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 3.3 v 4.0 v 349 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-47. atmega48a: minimum reset pulse width vs. v cc 8 5 c 25 c -40 c 0 200 400 600 8 00 1000 1200 1400 1600 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) p u lse w idth (ns) 350 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.2 atmega48pa typical characteristics 31.2.1 active supply current figure 31-48. atmega48pa: active supply current vs. low frequency (0.1-1.0mhz) figure 31-49. atmega48pa: active supply current vs. frequency (1-20mhz) 5.5v 5.0v 4.5v 4.0v 3 . 3 v 2.7v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 5.5v 5.0v 4.5v 0 1 2 3 4 5 6 7 8 9 10 11 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 4.0v 3 . 3 v 2.7v 1. 8 v 351 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-50. atmega48pa: active su pply current vs. v cc (internal rc oscillator, 128khz) figure 31-51. atmega48pa: active su pply current vs. v cc (internal rc oscillator, 1mhz) 105c 8 5c 25c -40c 0.005 0.01 0.015 0.02 0.025 0.0 3 0.0 3 5 0.04 0.045 0.05 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 1.1 1.2 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 352 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-52. atmega48pa: active su pply current vs. v cc (internal rc oscillator, 8mhz) 31.2.2 idle supply current figure 31-53. atmega48pa: idle supply current vs. low frequency (0.1-1.0mhz) 105c 8 5c 25c -40c 0.5 1 1.5 2 2.5 3 3 .5 4 4.5 5 5.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 5.5v 5.0v 4.5v 4.0v 3 . 3 v 2.7v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 353 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-54. atmega48pa: idle supply current vs. frequency (1-20mhz) figure 31-55. atmega48pa: idle supply current vs. v cc (internal rc os cillator, 128khz) 5.5v 5.0v 4.5v 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 2.6 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 4.0v 3 . 3 v 2.7v 1. 8 v 105c 8 5c 25c -40c 0.005 0.01 0.015 0.02 0.025 0.0 3 0.0 3 5 0.04 0.045 0.05 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 354 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-56. atmega48pa: idle supply current vs. v cc (internal rc oscillator, 1mhz) figure 31-57. atmega48pa: idle supply current vs. vcc (internal rc o scillator, 8mhz) 105c 8 5c 25c -40c 0.0 8 0.1 3 0.1 8 0.2 3 0.2 8 0. 33 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 1.1 1.2 1. 3 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 355 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.2.3 atmega48pa: supply current of io modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules are controlled by the power reduc- tion register. see ?power reduction register? on page 41 for details. it is possible to calculate the typical cu rrent consumption based on the numbers from table 31-4 on page 355 for other v cc and frequency settings than listed in table 31-3 on page 355 . 31.2.3.1 example calculate the expected current consumption in idle mode with timer1, adc, and spi enabled at v cc = 2.0v and f = 1mhz. from table 31-4 on page 355 , third column, we see that we need to add 11.2% for the timer1, 22.1% for the adc, and 17.6% for the spi module. reading from figure 31-53 on page 352 , we find that the idle current consumption is ~0.028 ma at v cc = 2.0v and f = 1mhz. the total current consumption in idle mode with timer1, adc, and spi enabled, gives: table 31-3. atmega48pa: additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz prusart0 2.9a 20.7a 97.4a prtwi 6.0a 44.8a 219.7a prtim2 5.0a 34.5a 141.3a prtim1 3.6a 24.4a 107.7a prtim0 1.4a 9.5a 38.4a prspi 5.0a 38.0a 190.4a pradc 6.1a 47.4a 244.7a table 31-4. atmega48pa: additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 31-48 on page 350 and figure 31-49 on page 350 ) additional current consumption compared to idle with external clock (see figure 31-53 on page 352 and figure 31-54 on page 353 ) prusart0 1.8% 11.4% prtwi 3.9% 20.6% prtim2 2.9% 15.7% prtim1 2.1% 11.2% prtim0 0.8% 4.2% prspi 3.3% 17.6% pradc 4.2% 22.1% i cc total 0.028 ma (1 + 0.112 + 0.221 + 0.176) ? 0.042 ma ?? 356 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.2.4 power-down supply current figure 31-58. atmega48pa: power-down supply current vs. v cc (watchdog timer disabled) figure 31-59. atmega48pa: power-down supply current vs. v cc (watchdog timer enabled) 105c 8 5c 25c -40c 0 0. 3 0.6 0. 9 1.2 1.5 1. 8 2.1 2.4 2.7 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 2.5 3 3 .5 4 4.5 5 5.5 6 6.5 7 7.5 8 8 .5 9 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 357 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.2.5 power-save supply current figure 31-60. atmega48pa: power-save supply current vs. v cc (watchdog timer disabled and 32khz crystal oscillator running) 31.2.6 standby supply current figure 31-61. atmega48pa: standby supply current vs. vcc (watchdog timer disabled) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 icc [a] vcc [v] 105c 8 5c 25c -40c 6mhz_xt a l 6mhz_re s 4mhz_xt a l 4mhz_re s 450khz_re s 2mhz_xt a l 2mhz_re s 1mhz_re s 0.0 15 3 0 45 60 75 9 0 105 120 1 3 5 150 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 358 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.2.7 pin pull-up figure 31-62. atmega48pa: i/o pin pull-up resistor current vs. input voltage (v cc = 1.8v) figure 31-63. atmega48pa: i/o pin pull-up resistor current vs. input voltage (v cc = 2.7v) 105c 8 5c 25c -40c 0 5 10 15 20 25 3 0 3 5 40 45 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v op (v) i op (a) 0 10 20 3 0 40 50 60 70 00. 3 0.6 0. 9 1.2 1.5 1. 8 2.1 2.4 2.7 v op (v) i op (a) 105c -40c 25c 8 5c 359 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-64. atmega48pa: i/o pin pull-up resistor current vs. input voltage (v cc = 5v) figure 31-65. atmega48pa: reset pull-up resistor current vs. reset pin voltage (v cc = 1.8v) 105c 8 5c 25c -40c 0 15 3 0 45 60 75 9 0 105 120 00.511.522.5 33 .5 4 4.5 5 v op (v) i op (a) 105c 8 5c 25c -40c 0 5 10 15 20 25 3 0 3 5 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v re s et (v) i re s et (a) 360 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-66. atmega48pa: reset pull-up resistor current vs. reset pin voltage (v cc = 2.7v) figure 31-67. atmega48pa: reset pull-up resistor current vs. reset pin voltage (v cc = 5v) 0 4 8 12 16 20 24 2 8 3 2 3 6 40 44 4 8 52 00. 3 0.6 0. 9 1.2 1.5 1. 8 2.1 2.4 2.7 v re s et (v) i re s et (a) 105c 8 5c 25c -40c 105c 8 5c 25c -40c 0 10 20 3 0 40 50 60 70 8 0 9 0 100 110 00.511.522.5 33 .5 4 4.5 5 v re s et (v) i re s et (a) 361 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.2.8 pin driver strength figure 31-68. atmega48pa: i/o pin output voltage vs. sink current (v cc = 3v) figure 31-69. atmega48pa: i/o pin output voltage vs. sink current (v cc = 5v) 105c 8 5c 25c -40c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol (v) 105c 8 5c 25c -40c 0 0.05 0.1 0.15 0.2 0.25 0. 3 0. 3 5 0.4 0.45 0.5 0.55 0.6 0.65 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol (v) 362 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-70. atmega48pa: i/o pin outp ut voltage vs. source current (vcc = 3v) figure 31-71. atmega48pa: i/o pin output voltage vs. source current (v cc = 5v) 105c 8 5c 25c -40c 1. 9 2 2.1 2.2 2. 3 2.4 2.5 2.6 2.7 2. 8 2. 9 3 0246 8 10 12 14 16 1 8 20 i oh (ma) v oh (v) 105c 8 5c 25c -40c 4. 3 4.4 4.5 4.6 4.7 4. 8 4. 9 5 0246 8 10 12 14 16 1 8 20 i oh (ma) v oh (v) 363 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.2.9 pin threshold and hysteresis figure 31-72. atmega48pa: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 31-73. atmega48pa: i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0?) 105c 8 5c 25c -40c 0. 8 1.1 1.4 1.7 2 2. 3 2.6 2. 9 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 105c 8 5c 25c -40c 0. 3 0.6 0. 9 1.2 1.5 1. 8 2.1 2.4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 364 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-74. atmega48pa: i/o pin input hysteresis vs. v cc figure 31-75. atmega48pa: reset input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) 105c 8 5c 25c -40c 0.25 0. 3 0. 3 5 0.4 0.45 0.5 0.55 0.6 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (mv) -40 c 105 c 8 5 c 25 c 105c 8 5c 25c -40c 0. 9 5 1.2 1.45 1.7 1. 9 5 2.2 2.45 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 105c 8 5c 25c -40c 365 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-76. atmega48pa: reset input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 31-77. atmega48pa: reset pin input hysteresis vs. v cc 105c 8 5c 25c -40c 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 105c 8 5c 25c -40c 0 0.05 0.1 0.15 0.2 0.25 0. 3 0. 3 5 0.4 0.45 0.5 0.55 0.6 0.65 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (mv) -40c 25c 105c 8 5c 366 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.2.10 bod threshold figure 31-78. atmega48pa: bod thresholds vs. temperature (bodlevel is 1.8v) figure 31-79. atmega48pa: bod thresholds vs. temperature (bodlevel is 2.7v) ri s ing vcc f a lling vcc 1.765 1.77 1.775 1.7 8 1.7 8 5 1.7 9 1.7 9 5 1. 8 1. 8 05 1. 8 1 1. 8 15 1. 8 2 1. 8 25 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) thre s hold (v) 2.64 2.65 2.66 2.67 2.6 8 2.6 9 2.7 2.71 2.72 2.7 3 2.74 2.75 2.76 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) thre s hold (v) ri s ing vcc f a lling vcc 367 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-80. atmega48pa: bod thresholds vs. temperature (bodlevel is 4.3v) figure 31-81. atmega48pa: bandgap voltage vs. v cc ri s ing vcc f a lling vcc 4.2 4.22 4.24 4.26 4.2 8 4. 3 4. 3 2 4. 3 4 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) thre s hold (v) 1.11 1.1125 1.115 1.1175 1.12 1.1225 1.125 1.1275 1.13 1.1325 1.522.533.54 4.5 5 5.5 bandgap voltage [v] vcc [v] 105c 8 5c 25c -40c 368 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.2.11 internal oscillator speed figure 31-82. atmega48pa: watchdog oscillato r frequency vs. temperature figure 31-83. atmega48pa: watchdog osc illator frequency vs. v cc 5.5v 4.0v 3 . 3 v 2.7v 104 106 10 8 110 112 114 116 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) f rc (khz) 105c 8 5c 25c -40c 104 106 10 8 110 112 114 116 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) f rc (khz) 369 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-84. atmega48pa: calibrat ed 8mhz rc oscillator frequency vs. v cc figure 31-85. atmega48pa: calibra ted 8mhz rc oscillator fr equency vs. temperature 105c 8 5c 25c -40c 7.65 7.7 7.75 7. 8 7. 8 5 7. 9 7. 9 5 8 8 .05 8 .1 8 .15 8 .2 8 .25 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) f rc (mhz) 5.5v 4.0v 3 .0v 1. 8 v 7.65 7.7 7.75 7. 8 7. 8 5 7. 9 7. 9 5 8 8 .05 8 .1 8 .15 8 .2 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) f rc (mhz) 370 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-86. atmega48pa: calibra ted 8mhz rc oscillator fr equency vs. osccal value 31.2.12 current consumption of peripheral units figure 31-87. atmega48pa: adc current vs. v cc (aref = av cc ) 105c 8 5c 25c -40c 4 5 6 7 8 9 10 11 12 1 3 14 15 016 3 24 8 64 8 0 9 611212 8 144 160 176 1 9 220 8 224 240 256 o s ccal (x1) f rc (mhz) 105c 8 5c 25c -40c 1 3 0 150 170 1 9 0 210 2 3 0 250 270 2 9 0 3 10 1.5 2 2.5 33 .544.555.5 v cc (v) i cc (a) 371 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-88. atmega48pa: analog comparator current vs. v cc figure 31-89. atmega48pa: aref external reference current vs. v cc 105c 8 5c 25c -40c 3 5 40 45 50 55 60 65 70 75 8 0 8 5 9 0 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) -40c 25c 8 5c 105c 105c 8 5c 25c -40c 40 50 60 70 8 0 9 0 100 110 120 1 3 0 140 150 1.5 2 2.5 33 .544.555.5 v cc (v) i cc (a) 372 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-90. atmega48pa: brownout detector current vs. v cc figure 31-91. atmega48pa: programming current vs. v cc 105c 8 5c 25c -40c 15 16 17 1 8 1 9 20 21 22 2 3 24 25 26 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 1 1.5 2 2.5 3 3 .5 4 4.5 5 5.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 373 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.2.13 current consumption in reset and reset pulsewidth figure 31-92. atmega48pa: reset supply current vs. low frequency (0.1mhz- 1.0mhz) figure 31-93. atmega48pa: reset supply current vs. frequency (1mhz- 20mhz) 5.5v 5.0v 4.5v 4.0v 3 . 3 v 2.7v 1. 8 v 0 0.01 0.02 0.0 3 0.04 0.05 0.06 0.07 0.0 8 0.0 9 0.1 0.11 0.12 0.1 3 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 5.5v 5.0v 4.5v 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7v 3 . 3 v 4.0v 374 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-94. atmega48pa: minimum reset pulse width vs. v cc 105c 8 5c 25c -40c 200 3 00 400 500 600 700 8 00 9 00 1000 1100 1200 1 3 00 1400 1500 1600 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) p u l s ewidth (n s ) 375 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.3 atmega88a typical characteristics 31.3.1 active supply current figure 31-95. atmega88a: active supply current vs. low frequency (0.1-1.0mhz) figure 31-96. atmega88a: active supply current vs. frequency (1 - 20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.2 0.4 0.6 0. 8 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 2 4 6 8 10 12 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1.8 v 2.7 v 3.3 v 4.0 v 376 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-97. atmega88a: active supply current vs. v cc (internal rc oscillator, 128khz) figure 31-98. atmega88a: active supply current vs. v cc (internal rc oscillator, 1mhz) 8 5 c 25 c -40 c 0 0.03 0.06 0.09 0.12 1.522.533.544.555.5 v cc ( v ) i cc (ma) 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 377 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-99. atmega88a: active supply current vs. v cc (internal rc oscillator, 8mhz) 31.3.2 idle supply current figure 31-100. atmega88a: idle supply current vs. low frequency (0.1-1.0mhz) 8 5 c 25 c -40 c 0 1 2 3 4 5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.03 0.06 0.09 0.12 0.15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 378 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-101. atmega88a: idle supply current vs. frequency (1-20mhz) figure 31-102. atmega88a: idle supply current vs. v cc (internal rc oscillator, 128khz) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 4.0 v 3.3 v 2.7 v 1. 8 v 8 5 c 25 c -40 c 0 0.01 0.02 0.03 0.04 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 379 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-103. atmega88a: idle supply current vs. v cc (internal rc oscillator, 1mhz) figure 31-104. atmega88a: idle supply current vs. vcc (internal rc oscillator, 8mhz) 8 5 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -40 c 0 0.3 0.6 0.9 1.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 380 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.3.3 atmega88a: supply current of io modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules are controlled by the power reduc- tion register. see ?power reduction register? on page 41 for details. it is possible to calculate the typical cu rrent consumption based on the numbers from table 31-8 on page 405 for other v cc and frequency settings than listed in table 31-7 on page 405 . 31.3.3.1 example calculate the expected current consumption in idle mode with timer1, adc, and spi enabled at v cc = 2.0v and f = 1mhz. from table 31-8 on page 405 , third column, we see that we need to add 13.6% for the timer1, 26.3% for the adc, and 21.5% for the spi module. reading from figure 31-147 on page 402 , we find that the idle current consumption is ~0.027 ma at v cc = 2.0v and f = 1mhz. the total current consumption in idle mode with timer1, adc, and spi enabled, gives: table 31-5. atmega88pa: additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz prusart0 3.0a 21.3a 97.9a prtwi 6.1a 45.4a 219.0a prtim2 5.2a 35.2a 149.5a prtim1 3.8a 25.6a 110.0a prtim0 1.5a 9.8a 39.6a prspi 5.2a 40.0a 199.6a pradc 6.3a 48.7a 247.0a table 31-6. atmega88pa: additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 31-142 on page 399 and figure 31-143 on page 400 ) additional current consumption compared to idle with external clock (see figure 31-147 on page 402 and figure 31-148 on page 402 ) prusart0 1.8% 11.4% prtwi 3.9% 24.4% prtim2 2.9% 18.6% prtim1 2.1% 13.6% prtim0 0.8% 5.2% prspi 3.5% 21.5% pradc 4.2% 26.3% i cc total 0.027 ma (1 + 0.136 + 0.263 + 0.215) ? 0.043 ma ?? 381 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.3.4 power-down supply current figure 31-105. atmega88a: power-down supply current vs. v cc (watchdog timer disabled) figure 31-106. atmega88a: power-down supply current vs. v cc (watchdog timer enabled) 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -40 c 0 2 4 6 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 382 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.3.5 power-save supply current figure 31-107. atmega88a: power-save supply current vs. v cc (watchdog timer disabled and 32khz crystal oscillator running) 31.3.6 standby supply current figure 31-108. atmega88a: standby supply current vs. vcc (watchdog timer disabled) 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) 8 5 c 25 c -40 c 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0.1 8 1.522.533.544.555.5 v cc ( v ) i cc (ma) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 450khz_res 2mhz_xtal 2mhz_res 383 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.3.7 pin pull-up figure 31-109. atmega88a: i/o pin pull-up resistor current vs. input voltage (v cc = 1.8 v) figure 31-110. atmega88a: i/o pin pull-up resistor current vs. input voltage (v cc = 2.7 v) 8 5 c 25 c -40 c 0 10 20 30 40 50 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v op ( v ) i op ( u a) 8 5 c 25 c -40 c 0 10 20 30 40 50 60 70 8 0 0 0.5 1 1.5 2 2.5 3 v op ( v ) i op ( u a) 384 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-111. atmega88a: i/o pin pull-up resistor current vs. input voltage (v cc = 5 v) figure 31-112. atmega88a: reset pull-up resistor current vs. rese t pin voltage (v cc = 1.8 v) 8 5 c 25 c -40 c 0 20 40 60 8 0 100 120 140 012345 v op ( v ) i op ( u a) 8 5 c 25 c -40 c 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v reset ( v ) i reset ( u a) 385 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-113. atmega88a: reset pull-up resistor current vs. rese t pin voltage (v cc = 2.7 v) figure 31-114. atmega88a: reset pull-up resistor current vs. rese t pin voltage (v cc = 5 v) 8 5 c 0 10 20 30 40 50 60 0 0.5 1 1.5 2 2.5 3 v reset ( v ) i reset ( u a) -40 c 25 c 8 5 c -40 c 25 c 0 20 40 60 8 0 100 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v reset ( v ) i reset ( u a) 386 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.3.8 pin driver strength figure 31-115. atmega88a: i/o pin output voltage vs. sink current (v cc = 3 v) figure 31-116. atmega88a: i/o pin output voltage vs. sink current (v cc = 5 v) 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 04 8 12 16 20 i ol (ma) v ol ( v ) 8 5 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 04 8 12 16 20 i ol (ma) v ol ( v ) 387 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-117. atmega88a: i/o pin output voltage vs. source current (vcc = 3 v) figure 31-118. )atmega88a: i/o pin output voltage vs. source current (v cc = 5 v) 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 3.5 04 8 12 16 20 i oh (ma) v oh ( v ) 8 5 c 25 c -40 c 4.2 4.3 4.4 4.5 4.6 4.7 4. 8 4.9 5 04 8 12 16 20 i oh (ma) v oh ( v ) 388 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.3.9 pin threshold and hysteresis figure 31-119. atmega88a: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 31-120. atmega88a: i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0? 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) , 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 389 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-121. atmega88a: i/o pin input hysteresis vs. v cc figure 31-122. atmega88a: reset input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (v) 8 5 c 25 c -40 c 0 0.3 0.6 0.9 1.2 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 390 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-123. atmega88a: reset input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 31-124. atmega88a: reset pin input hysteresis vs. v cc 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (v) 391 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.3.10 bod threshold figure 31-125. atmega88a: bod thresholds vs. temperature (bodlevel is 1.8 v) figure 31-126. atmega88a: bod thresholds vs. temperature (bodlevel is 2.7 v) rising v cc falling v cc 1.77 1.7 8 1.79 1. 8 1. 8 1 1. 8 2 1. 8 3 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re (c) threshold ( v ) rising v cc falling v cc 2.64 2.66 2.6 8 2.7 2.72 2.74 2.76 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re (c) threshold ( v ) 392 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-127. atmega88a: bod thresholds vs. temperature (bodlevel is 4.3 v) figure 31-128. atmega88a: bandgap voltage vs. v cc rising v cc falling v cc 4.22 4.24 4.26 4.2 8 4.3 4.32 4.34 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re (c) threshold ( v ) 8 5 c 25 c -40 c 1.096 1.097 1.09 8 1.099 1.1 1.101 1.102 1.103 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) bandgap v oltage ( v ) 393 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.3.11 internal oscillator speed figure 31-129. atmega88a: watchdog oscillator frequency vs. temperature figure 31-130. atmega88a: watchdog osc illator frequency vs. v cc 5.5 v 4.0 v 3.3 v 2.7 v 105 106 107 10 8 109 110 111 112 113 114 -40 -20 0 20 40 60 8 0 100 temperat u re (c) f rc (khz) 8 5 c 25 c -40 c 104 106 10 8 110 112 114 116 1.522.533.544.555.5 v cc ( v ) f rc (khz) 394 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-131. atmega88a: calibrated 8mhz rc oscillator frequency vs. v cc figure 31-132. atmega88a: calibrated 8mhz rc osc illator frequency vs. temperature 8 5 c 25 c -40 c 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 8 .3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) f rc (mhz) 5.5 v 4.0 v 3.0 v 7. 8 7.9 8 8 .1 8 .2 8 .3 -40 -20 0 20 40 60 8 0 100 temperat u re (c) f rc (mhz) 395 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-133. atmega88a: calibrated 8mhz rc osc illator frequency vs. osccal value 31.3.12 current consumption of peripheral units figure 31-134. atmega88a: adc current vs. v cc (aref = av cc ) 8 5 c 25 c -40 c 0 2 4 6 8 10 12 14 016324 8 64 8 09611212 8 144 160 176 192 20 8 224 240 256 osccal (x1) f rc (mhz) 8 5 c 25 c -40 c 0 50 100 150 200 250 300 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 396 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-135. atmega88a: analog comparator current vs. v cc figure 31-136. atmega88a: aref external reference current vs. v cc 8 5 c 25 c -40 c 0 10 20 30 40 50 60 70 8 0 90 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -40 c 0 20 40 60 8 0 100 120 140 160 1.522.533.544.555.5 v cc ( v ) i cc ( u a) 397 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-137. atmega88a: brownout detector current vs. v cc figure 31-138. atmega88a: programming current vs. v cc 8 5 c 25 c -40 c 0 10 20 30 40 50 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -40 c 0 1 2 3 4 5 6 7 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 398 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.3.13 current consumption in reset and reset pulsewidth figure 31-139. atmega88a: reset supply current vs. low frequency (0.1 - 1.0mhz) figure 31-140. atmega88a: reset supply current vs. frequency (1 - 20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 0.4 0. 8 1.2 1.6 2 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 4.0 v 3.3 v 399 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-141. atmega88a: minimum reset pulse width vs. v cc 31.4 atmega88pa typical characteristics 31.4.1 active supply current figure 31-142. atmega88pa: active supply current vs. low frequency (0.1-1.0mhz) 8 5 c 25 c -40 c 0 200 400 600 8 00 1000 1200 1400 1600 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) p u lse w idth (ns) 5.5v 5.0v 4.5v 4.0v 3 . 3 v 2.7v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 400 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-143. atmega88pa: active supply current vs. frequency (1 - 20mhz) figure 31-144. atmega88pa: active supply current vs. v cc (internal rc oscillator, 128khz) 5.5v 5.0v 4.5v 0 2 4 6 8 10 12 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 4.0v 3 . 3 v 2.7v 1. 8 v 105c 8 5c 25c -40c 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 401 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-145. atmega88pa: active supply current vs. v cc (internal rc o scillator, 1mhz) figure 31-146. atmega88pa: active supply current vs. v cc (internal rc o scillator, 8mhz) 105c 8 5c 25c -40c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 0 1 2 3 4 5 6 1.5 2 2.5 33 .544.555.5 v cc (v) i cc (ma) 402 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.4.2 idle supply current figure 31-147. atmega88pa: idle supply current vs. low frequency (0.1-1.0mhz) figure 31-148. atmega88pa: idle supply current vs. frequency (1 - 20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.03 0.06 0.09 0.12 0.15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 4.0 v 3.3 v 2.7 v 1. 8 v 403 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-149. atmega88pa: idle supply current vs. v cc (internal rc oscillator, 128khz) figure 31-150. atmega88pa: idle supply current vs. v cc (internal rc oscillator, 1mhz) 105c 8 5c 25c -40c 0 0.005 0.01 0.015 0.02 0.025 0.0 3 0.0 3 5 0.04 0.045 0.05 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 0 0.05 0.1 0.15 0.2 0.25 0. 3 0. 3 5 0.4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 404 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-151. atmega88pa: idle supply current vs. v cc (internal rc oscillator, 8mhz) 105c 8 5c 25c -40c 0 0.2 0.4 0.6 0. 8 1 1.2 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 405 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.4.3 atmega88pa: supply current of io modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules are controlled by the power reduc- tion register. see ?power reduction register? on page 41 for details. it is possible to calculate the typical cu rrent consumption based on the numbers from table 31-8 for other v cc and frequency settings than listed in table 31-7 . 31.4.3.1 example calculate the expected current consumption in idle mode with timer1, adc, and spi enabled at v cc = 2.0v and f = 1mhz. from table 31-8 , third column, we see that we need to add 13.6% for the timer1, 26.3% for the adc, and 21.5% for the spi module. reading from figure 31-147 on page 402 , we find that the idle current consumption is ~0.027 ma at v cc = 2.0v and f = 1mhz. the total current consumption in idle mode with timer1, adc, and spi enabled, gives: table 31-7. atmega88pa: additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz prusart0 3.0a 21.3a 97.9a prtwi 6.1a 45.4a 219.0a prtim2 5.2a 35.2a 149.5a prtim1 3.8a 25.6a 110.0a prtim0 1.5a 9.8a 39.6a prspi 5.2a 40.0a 199.6a pradc 6.3a 48.7a 247.0a table 31-8. atmega88pa: additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 31-142 on page 399 and figure 31-143 on page 400 ) additional current consumption compared to idle with external clock (see figure 31-147 on page 402 and figure 31-148 on page 402 ) prusart0 1.8% 11.4% prtwi 3.9% 24.4% prtim2 2.9% 18.6% prtim1 2.1% 13.6% prtim0 0.8% 5.2% prspi 3.5% 21.5% pradc 4.2% 26.3% i cc total 0.027 ma (1 + 0.136 + 0.263 + 0.215) ? 0.043 ma ?? 406 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.4.4 power-down supply current figure 31-152. atmega88pa: power-down supply current vs. v cc (watchdog timer disabled) figure 31-153. atmega88pa: power-down supply current vs. v cc (watchdog timer enabled) 105c 8 5c 25c -40c 0 1 2 3 4 5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 0 2 4 6 8 10 12 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 407 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.4.5 power-save supply current figure 31-154. atmega88pa: power-save supply current vs. v cc (watchdog timer disabled and 32khz crystal oscillator running) 31.4.6 standby supply current figure 31-155. atmega88pa: standby supply current vs. vcc (watchdog timer disabled) 105c 8 5c 25c -40c 0 2 4 6 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0.1 8 1.522.533.544.555.5 v cc ( v ) i cc (ma) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 450khz_res 2mhz_xtal 2mhz_res 408 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.4.7 pin pull-up figure 31-156. atmega88pa: i/o pin pull-up resistor current vs. input voltage (v cc = 1.8v) figure 31-157. atmega88pa: i/o pin pull-up resistor current vs. input voltage (v cc = 2.7v) 105c 8 5c 25c -40c 0 10 20 3 0 40 50 60 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 v op (v) i op (a) 105c 8 5c 25c -40c 0 10 20 3 0 40 50 60 70 8 0 0 0.5 1 1.5 2 2.5 3 v op (v) i op (a) 409 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-158. atmega88pa: i/o pin pull-up resistor current vs. input voltage (v cc = 5v) figure 31-159. atmega88pa: reset pull-up resistor current vs. reset pin voltage (v cc = 1.8v) 0 20 40 60 8 0 100 120 140 160 012 3 456 v op (v) i op (a) 105c 8 5c 25c -40c 105c 8 5c 25c -40c 0 5 10 15 20 25 3 0 3 5 40 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 v re s et (v) i re s et (a) 410 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-160. atmega88pa: reset pull-up resistor current vs. reset pin voltage (v cc = 2.7v) figure 31-161. atmega88pa: reset pull-up resistor current vs. reset pin voltage (v cc = 5v) 0 10 20 3 0 40 50 60 0 0.5 1 1.5 2 2.5 3 v re s et (v) i re s et (a) 105c 8 5c 25c -40c 0 20 40 60 8 0 100 120 012 3 456 v re s et (v) i re s et (a) 105c 8 5c 25c -40c 411 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.4.8 pin driver strength figure 31-162. atmega88pa: i/o pin output voltage vs. sink current (v cc = 3v) figure 31-163. atmega88pa: i/o pin output voltage vs. sink current (v cc = 5v) 105c 8 5c 25c -40c 0 0.2 0.4 0.6 0. 8 1 1.2 0 5 10 15 20 25 i ol (ma) v ol (v) 105c 8 5c 25c -40c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0 5 10 15 20 25 i ol (ma) v ol (v) 412 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-164. atmega88pa: i/o pin output voltage vs. source current (vcc = 3v) figure 31-165. atmega88pa: i/o pin output voltage vs. source current (v cc = 5v) 105c 8 5c 25c -40c 1.5 2 2.5 3 3 .5 0 5 10 15 20 25 i oh (ma) v oh (v) 105c 8 5c 25c -40c 4.2 4.4 4.6 4. 8 5 5.2 0 5 10 15 20 25 i oh (ma) v oh (v) 413 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.4.9 pin threshold and hysteresis figure 31-166. atmega88pa: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 31-167. atmega88pa: i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0?) 105c 8 5c 25c -40c 0 0.5 1 1.5 2 2.5 3 3 .5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 105c 8 5c 25c -40c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 414 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-168. atmega88pa: i/o pin input hysteresis vs. v cc figure 31-169. atmega88pa: reset input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) 105c 8 5c 25c -40c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 1.5 2 2.5 33 .544.555.5 v cc (v) inp u t hy s tere s i s (mv) 105c 8 5c 25c -40c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 415 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-170. atmega88pa: reset input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 31-171. atmega88pa: reset pin input hysteresis vs. v cc 105c 8 5c 25c -40c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 105c 8 5c 25c -40c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (mv) 416 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.4.10 bod threshold figure 31-172. atmega88pa: bod thresholds vs. temperature (bodlevel is 1.8v) figure 31-173. atmega88pa: bod thresholds vs. temperature (bodlevel is 2.7v) ri s ing vcc f a lling vcc 1.76 1.77 1.7 8 1.7 9 1. 8 1. 8 1 1. 8 2 1. 83 1. 8 4 -60 -40 -20 0 20 40 60 8 0 100 120 temper a t u re (c) thre s hold (v) ri s ing vcc f a lling vcc 2.6 2.62 2.64 2.66 2.6 8 2.7 2.72 2.74 2.76 2.7 8 2. 8 -60 -40 -20 0 20 40 60 8 0 100 120 temper a t u re (c) thre s hold (v) 417 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-174. atmega88pa: bod thresholds vs. temperature (bodlevel is 4.3v) figure 31-175. atmega88pa: calibrated bandgap voltage vs. temperature ri s ing vcc f a lling vcc 4 4.05 4.1 4.15 4.2 4.25 4. 3 4. 3 5 4.4 4.45 4.5 -60 -40 -20 0 20 40 60 8 0100120 temper a t u re (c) thre s hold (v) 1.045 1.05 1.055 1.06 1.065 1.07 1.075 1.08 1.085 1.09 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 bandgap voltage [v] temperature [v] 5.5 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8v 418 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-176. atmega88pa: bandgap voltage vs. v cc 31.4.11 internal oscillator speed figure 31-177. atmega88pa: watchdog oscillato r frequency vs. temperature 1.045 1.05 1.055 1.06 1.065 1.07 1.075 1.08 1.085 1.09 1.5 2 2.5 3 3.5 4 4.5 5 5.5 bandgap voltage [v] vcc [v] 105c 8 5c 25c -40c 5.5v 4.0v 3 . 3 v 2.7v 102 104 106 10 8 110 112 114 116 -40 -20 0 20 40 60 8 0 100 120 temper a t u re (c) f rc (khz) 419 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-178. atmega88pa: watchdog osc illator frequency vs. v cc figure 31-179. atmega88pa: calibrated 8mhz rc oscillator frequency vs. v cc 105c 8 5c 25c -40c 102 104 106 10 8 110 112 114 116 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) f rc (khz) 105c 8 5c 25c -40c 7.5 7.75 8 8 .25 8 .5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) f rc (mhz) 420 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-180. atmega88pa: calibrated 8mhz rc oscillator frequency vs. temperature figure 31-181. atmega88pa: calibrated 8mhz rc os cillator frequency vs. osccal value 5.5v 4.0v 3 .0v 1. 8 v 7.6 7.7 7. 8 7. 9 8 8 .1 8 .2 8 . 3 8 .4 -60 -40 -20 0 20 40 60 8 0100120 temper a t u re (c) f rc (mhz) 105c 8 5c 25c -40c 0 2 4 6 8 10 12 14 016324 8 64 8 0 96 112 12 8 144 160 176 192 20 8 224 240 256 osccal (x1) f rc (mhz) 421 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.4.12 current consumption of peripheral units figure 31-182. atmega88pa: adc current vs. v cc (aref = av cc ) figure 31-183. atmega88pa: analog comparator current vs. v cc 105c 8 5c 25c -40c 0 50 100 150 200 250 3 00 3 50 1.522.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 0 10 20 3 0 40 50 60 70 8 0 9 0 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 422 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-184. atmega88pa: aref external reference current vs. v cc figure 31-185. atmega88pa: brownout detector current vs. v cc 105c 8 5c 25c -40c 0 20 40 60 8 0 100 120 140 160 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 0 5 10 15 20 25 3 0 1.5 2 2.5 33 .544.555.5 v cc (v) i cc (a) 423 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-186. atmega88pa: programming current vs. v cc 31.4.13 current consumption in reset and reset pulsewidth figure 31-187. atmega88pa: reset supply current vs. low frequency (0.1mhz - 1.0mhz) 105c 8 5c 25c -40c 0 1 2 3 4 5 6 7 8 9 10 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 5.5v 5.0v 4.5v 4.0v 3 . 3 v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 424 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-188. atmega88pa: reset supply current vs. frequency (1mhz - 20mhz) figure 31-189. atmega88pa: minimum re set pulse width vs. v cc 5.5v 5.0v 4.5v 0 0.5 1 1.5 2 2.5 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 4.0v 3 . 3 v 2.7v 1. 8 v 105c 8 5c 25c -40c 0 200 400 600 8 00 1000 1200 1400 1600 1 8 00 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) p u l s ewidth (n s ) 425 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.5 atmega168a typical characteristics 31.5.1 active supply current figure 31-190. atmega168a: active supply current vs. low frequency (0.1-1.0mhz) figure 31-191. atmega168a: active supply current vs. frequency (1-20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.2 0.4 0.6 0. 8 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 2 4 6 8 10 12 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 4.0 v 3.3 v 2.7 v 426 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-192. atmega168a: active supply current vs. v cc (internal rc osc illator, 128khz) figure 31-193. atmega168a: active supply current vs. v cc (internal rc os cillator, 1mhz) 8 5 c 25 c -40 c 0 0.03 0.06 0.09 0.12 0.15 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 427 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-194. atmega168a: active supply current vs. v cc (internal rc os cillator, 8mhz) 31.5.2 idle supply current figure 31-195. atmega168a: idle supply current vs. low frequency (0.1-1.0mhz) 25 c -40 c 0 1 2 3 4 5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.03 0.06 0.09 0.12 0.15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 428 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-196. atmega168a: idle supply current vs. frequency (1-20mhz) figure 31-197. iatmega168a: idle supply current vs. v cc (internal rc oscillator, 128khz) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 3 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 4.0 v 3.3 v 8 5 c 25 c -40 c 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 429 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-198. atmega168a: idle supply current vs. v cc (internal rc oscillator, 1mhz) figure 31-199. atmega168a: idle supply current vs. vcc (internal rc oscillator, 8mhz) 8 5 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -40 c 0 0.3 0.6 0.9 1.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 430 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.5.3 atmega168a supply current of io modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules are controlled by the power reduc- tion register. see ?power reduction register? on page 41 for details. it is possible to calculate the typical current consumption based on the numbers from table 31-12 on page 455 for other v cc and frequency settings than listed in table 31-11 on page 455 . 31.5.3.1 example calculate the expected current consumption in idle mode with timer1, adc, and spi enabled at v cc = 2.0v and f = 1mhz. from table 31-12 on page 455 , third column, we see that we need to add 10.3% for the timer1, 20.3% for the adc, and 17.1% for the spi module. reading from figure 31-242 on page 452 , we find that the idle current consumption is ~0.027 ma at v cc = 2.0v and f = 1mhz. the total current consumption in idle mode with timer1, adc, and spi enabled, gives: table 31-9. atmega168a: additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz prusart0 2.86a 20.3a 52.2a prtwi 6.00a 44.1a 122.0a prtim2 4.97a 33.2a 79.8a prtim1 3.50a 23.0a 55.3a prtim0 1.43a 9.2a 21.4a prspi 5.01a 38.6a 111.4a pradc 6.34a 45.7a 123.6a table 31-10. atmega168a: additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 31-237 on page 450 and figure 31-238 on page 450 ) additional current consumption compared to idle with external clock (see figure 31-242 on page 452 and figure 31-243 on page 453 ) prusart0 1.5% 8.9% prtwi 3.2% 19.5% prtim2 2.4% 14.8% prtim1 1.7% 10.3% prtim0 0.7% 4.1% prspi 2.9% 17.1% pradc 3.4% 20.3% i cc total 0.027 ma (1 + 0.103 + 0.203 + 0.171) ? 0.040 ma ?? 431 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.5.4 power-down supply current figure 31-200. atmega168a: power-down supply current vs. v cc (watchdog timer disabled) figure 31-201. atmega168a: power-down supply current vs. v cc (watchdog timer enabled) 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -40 c 0 2 4 6 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 432 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.5.5 power-save supply current figure 31-202. atmega168a: power-save supply current vs. v cc (watchdog timer disabled and 32khz crystal oscillator running) 31.5.6 standby supply current figure 31-203. atmega168a: standby supply current vs. vcc (watchdog timer disabled) 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 450khz_res 2mhz_xtal 2mhz_res 1mhz_res 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (mhz) i cc (ma) 433 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.5.7 pin pull-up figure 31-204. atmega168a: i/o pin pull-up resistor current vs. input voltage (v cc = 1.8 v) figure 31-205. atmega168a: i/o pin pull-up resistor current vs. input voltage (v cc = 2.7 v) 8 5 c 25 c -40 c 0 10 20 30 40 50 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 v op ( v ) i op ( u a) 8 5 c 25 c -40 c 0 10 20 30 40 50 60 70 8 0 0 0.5 1 1.5 2 2.5 3 v op ( v ) i op ( u a) 434 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-206. atmega168a: i/o pin pull-up resistor current vs. input voltage (v cc = 5 v) figure 31-207. atmega168a: reset pull-up resistor current vs. reset pin voltage (v cc =1.8v) 8 5 c 25 c -40 c 0 20 40 60 8 0 100 120 140 160 0123456 v op ( v ) i op ( u a) 8 5 c 25 c -40 c 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v reset ( v ) i reset ( u a) 435 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-208. atmega168a: reset pull-up resistor current vs. reset pin voltage (v cc =2.7v) figure 31-209. atmega168a: reset pull-up resistor current vs. reset pin voltage (v cc =5v) 8 5 c 0 10 20 30 40 50 60 0 0.5 1 1.5 2 2.5 3 v reset ( v ) i reset ( u a) -40 c 25 c 0 20 40 60 8 0 100 120 012345 v reset ( v ) i reset ( u a) 8 5 c -40 c 25 c 436 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.5.8 pin driver strength figure 31-210. atmega168a: i/o pin output voltage vs. sink current (v cc = 3 v) figure 31-211. atmega168a: i/o pin output voltage vs. sink current (v cc = 5 v) 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 04 8 12 16 20 i ol (ma) v ol ( v ) 8 5 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 04 8 12 16 20 i ol (ma) v ol ( v ) 437 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-212. atmega168a: i/o pin output voltage vs. source current (vcc = 3 v) figure 31-213. atmega168a: i/o pin output voltage vs. source current (v cc = 5 v) 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 3.5 04 8 12 16 20 i oh (ma) v oh ( v ) 8 5 c 25 c -40 c 4 4.2 4.4 4.6 4. 8 5 04 8 12 16 20 i oh (ma) v oh ( v ) 438 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.5.9 pin threshold and hysteresis figure 31-214. atmega168a: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 31-215. atmega168a: i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0?) 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 439 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-216. atmega168a: i/o pin input hysteresis vs. v cc figure 31-217. atmega168a: reset input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (v) 8 5 c 25 c -40 c 0 0.3 0.6 0.9 1.2 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 440 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-218. atmega168a: reset input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 31-219. atmega168a: reset pin input hysteresis vs. v cc 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (v) 441 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.5.10 bod threshold figure 31-220. atmega168a: bod thresholds vs. te mperature (bodlevel is 1.8 v) figure 31-221. atmega168a: bod thresholds vs. te mperature (bodlevel is 2.7 v) rising v cc falling v cc 1.72 1.74 1.76 1.7 8 1. 8 1. 8 2 1. 8 4 1. 8 6 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re (c) threshold ( v ) rising v cc falling v cc 2.62 2.64 2.66 2.6 8 2.7 2.72 2.74 2.76 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re ( c) threshold ( v ) 442 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-222. atmega168a: bod thresholds vs. te mperature (bodlevel is 4.3 v) figure 31-223. atmega168a: bandgap voltage vs. v cc rising v cc falling v cc 4.2 4.22 4.24 4.26 4.2 8 4.3 4.32 4.34 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re (c) threshold ( v ) 8 5 c 25 c -40 c 1.115 1.117 1.119 1.121 1.123 1.125 1.127 1.129 1.131 1.133 1.135 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) bandgap v oltage ( v ) 443 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.5.11 internal oscillator speed figure 31-224. atmega168a: watchdog oscillato r frequency vs . temperature figure 31-225. atmega168a: watchdog osc illator frequency vs. v cc 5.5 v 3.3 v 2.7 v 111 113 115 117 119 121 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re (c) f rc (khz) 8 5 c 25 c -40 c 110 112 114 116 11 8 120 122 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) f rc (khz) 444 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-226. atmega168a: calibrated 8mhz rc oscillator frequency vs. v cc figure 31-227. atmega168a: calibrated 8mhz rc osc illator frequency vs. temperature 8 5 c 25 c -40 c 7.4 7.6 7. 8 8 8 .2 8 ,4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) f rc (mhz) 5.5 v 5.0 v 2.7 v 1. 8 v 7.5 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 8 .3 -50-40-30-20-10 0 10203040506070 8 090 temperat u re (c) f rc (mhz) 445 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-228. atmega168a: calibrated 8mhz rc osc illator frequency vs. osccal value 31.5.12 current consumption of peripheral units figure 31-229. atmega168a: adc current vs. v cc (aref = av cc ) 8 5 c 25 c -40 c 0 2 4 6 8 10 12 14 16 016324 8 64 8 09611212 8 144 160 176 192 20 8 224 240 256 osccal (x1) f rc (mhz) 8 5 c 25 c -40 c 100 150 200 250 300 350 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 446 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-230. atmega168a: analog comparator current vs. v cc figure 31-231. atmega168a: aref external reference current vs. v cc 8 5 c 25 c -40 c 30 40 50 60 70 8 0 90 1.522.533.544.555.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -40 c 0 20 40 60 8 0 100 120 140 160 1 8 0 1.522.533.544.555.5 v cc ( v ) i cc ( u a) 447 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-232. atmega168a: brownout detector current vs. v cc figure 31-233. atmega168a: programming current vs. v cc 8 5 c 25 c -40 c 12 14 16 1 8 20 22 24 26 1.522.533.544.555.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -40 c 0 2 4 6 8 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 448 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.5.13 current consumption in reset and reset pulsewidth figure 31-234. atmega168a: reset supply current vs. low frequency (0.1 - 1.0mhz) figure 31-235. atmega168a: reset supply current vs. frequency (1 - 20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 3.3 v 4.0 v 449 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-236. atmega168a: minimum reset pulse width vs. v cc 8 5 c 25 c -40 c 0 250 500 750 1000 1250 1500 1750 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) p u lse w idth (ns) 450 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.6 atmega168pa typical characteristics 31.6.1 active supply current figure 31-237. atmega168pa: active supply current vs. low frequency (0.1-1.0mhz) figure 31-238. atmega168pa: active supply current vs. frequency (1-20mhz) 5.5v 5.0v 4.5v 4.0v 3 . 3 v 2.7v 1. 8 v 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 5.5v 5.0v 4.5v 0 2 4 6 8 10 12 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7v 3 .6v 4.0v 451 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-239. atmega168pa: active supply current vs. v cc (internal rc oscillator, 128khz) figure 31-240. atmega168pa: active supply current vs. v cc (internal rc oscillator, 1mhz) 105c 8 5c 25c -40c 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 1.1 1.2 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 452 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-241. atmega168pa: active supply current vs. v cc (internal rc oscillator, 8mhz) 31.6.2 idle supply current figure 31-242. atmega168pa: idle supply current vs. low frequency (0.1-1.0mhz) 105c 8 5c 25c -40c 0.5 1 1.5 2 2.5 3 3 .5 4 4.5 5 5.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 5.5v 5.0v 4.5v 4.0v 3 .6v 2.7v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 453 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-243. atmega168pa: idle supply current vs. frequency (1-20mhz) figure 31-244. atmega168pa: idle supply current vs. v cc (internal rc osc illator, 128khz) 5.5v 5.0v 4.5v 0 2 4 6 8 10 12 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7v 3 .6v 4.0v 105c 8 5c 25c -40c 0.005 0.01 0.015 0.02 0.025 0.0 3 0.0 3 5 0.04 0.045 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 454 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-245. atmega168pa: idle supply current vs. v cc (internal rc os cillator, 1mhz) figure 31-246. atmega168pa: idle supply current vs. v cc (internal rc os cillator, 8mhz) 105c 8 5c 25c -40c 0.06 0.0 9 0.12 0.15 0.1 8 0.21 0.24 0.27 0. 3 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 0.1 0. 3 0.5 0.7 0. 9 1.1 1. 3 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 455 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.6.3 atmega168pa supply current of io modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules are controlled by the power reduc- tion register. see ?power reduction register? on page 41 for details. it is possible to calculate the typical current consumption based on the numbers from table 31-12 on page 455 for other v cc and frequency settings than listed in table 31-11 on page 455 . 31.6.3.1 example calculate the expected current consumption in idle mode with timer1, adc, and spi enabled at v cc = 2.0v and f = 1mhz. from table 31-12 on page 455 , third column, we see that we need to add 10.3% for the timer1, 20.3% for the adc, and 17.1% for the spi module. reading from figure 31-242 on page 452 , we find that the idle current consumption is ~0.027 ma at v cc = 2.0v and f = 1mhz. the total current consumption in idle mode with timer1, adc, and spi enabled, gives: table 31-11. atmega168pa: additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz prusart0 2.86a 20.3a 52.2a prtwi 6.00a 44.1a 122.0a prtim2 4.97a 33.2a 79.8a prtim1 3.50a 23.0a 55.3a prtim0 1.43a 9.2a 21.4a prspi 5.01a 38.6a 111.4a pradc 6.34a 45.7a 123.6a table 31-12. atmega168pa: additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 31-237 on page 450 and figure 31-238 on page 450 ) additional current consumption compared to idle with external clock (see figure 31-242 on page 452 and figure 31-243 on page 453 ) prusart0 1.5% 8.9% prtwi 3.2% 19.5% prtim2 2.4% 14.8% prtim1 1.7% 10.3% prtim0 0.7% 4.1% prspi 2.9% 17.1% pradc 3.4% 20.3% i cc total 0.02 ma (1 + 0.103 + 0.203 + 0.171) ? 0.04 ma ?? 456 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.6.4 power-down supply current figure 31-247. atmega168pa: power-down supply current vs. v cc (watchdog timer disabled) figure 31-248. atmega168pa: power-down supply current vs. v cc (watchdog timer enabled) 105c 8 5c 25c -40c 0 0. 3 0.6 0. 9 1.2 1.5 1. 8 2.1 2.4 1.5 2 2.5 33 .544.555.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 3 4 5 6 7 8 9 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 457 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.6.5 power-save supply current figure 31-249. atmega168pa: power-save supply current vs. v cc (watchdog timer disabled and 32khz crystal oscillator running) 31.6.6 standby supply current figure 31-250. atmega168pa: standby supply current vs. vcc (watchdog timer disabled) 105c 8 5c 25c -40c 0.5 1 1.5 2 2.5 3 3 .5 4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 450khz_res 2mhz_xtal 2mhz_res 1mhz_res 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (mhz) i cc (ma) 458 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.6.7 pin pull-up figure 31-251. atmega168pa: i/o pin pull-up resistor current vs. input voltage (v cc = 1.8v) figure 31-252. atmega168pa: i/o pin pull-up resistor current vs. input voltage (v cc = 2.7v) 105c 8 5c 25c -40c 0 5 10 15 20 25 3 0 3 5 40 45 50 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v op (v) i op (a) 105c 8 5c 25c -40c 0 10 20 3 0 40 50 60 70 8 0 0 0.5 1 1.5 2 2.5 3 v op (v) i op (a) 459 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-253. atmega168pa: i/o pin pull-up resistor current vs. input voltage (v cc = 5v) figure 31-254. atmega168pa: reset pull-up resistor current vs. reset pin voltage (v cc = 1.8v) 105c 8 5c 25c 0 20 40 60 8 0 100 120 140 012 3 45 v op (v) i op (a) -40c 105c 8 5c 25c -40c 0 5 10 15 20 25 3 0 3 5 40 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v re s et (v) i re s et (a) 460 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-255. atmega168pa: reset pull-up resistor current vs. reset pin voltage (v cc = 2.7v) figure 31-256. atmega168pa: reset pull-up resistor current vs. reset pin voltage (v cc = 5v) 105 c 8 5c 25c -40c 0 10 20 3 0 40 50 60 00. 3 0.6 0. 9 1.2 1.5 1. 8 2.1 2.4 2.7 v re s et (v) i re s et (a) 105c 8 5c 25c -40c 0 20 40 60 8 0 100 120 00.511.522.5 33 .5 4 4.5 5 v re s et (v) i re s et (a) 461 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.6.8 pin driver strength figure 31-257. atmega168pa: i/o pin output voltage vs. sink current (v cc = 3v) figure 31-258. atmega168pa: i/o pin output voltage vs. sink current (v cc = 5v) 105c 8 5c 25c -40c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol (v) 105c 8 5c 25c -40c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol (v) 462 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-259. atmega168pa: i/o pin output voltage vs. source current (v cc = 3v) figure 31-260. atmega168pa i/o pin output voltage vs. source current (v cc = 5v) 105c 8 5c 25c -40c 1.7 1. 9 2.1 2. 3 2.5 2.7 2. 9 3 .1 0 5 10 15 20 i oh (ma) v oh (v) 105c 8 5c 25c -40c 4. 3 4.4 4.5 4.6 4.7 4. 8 4. 9 5 0 5 10 15 20 i oh (ma) v oh (v) 463 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.6.9 pin threshold and hysteresis figure 31-261. atmega168pa i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 31-262. atmega168pa i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0?) 105c 8 5c 25c -40c 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 105c 8 5c 25c -40c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 464 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-263. atmega168pa i/o pin input hysteresis vs. v cc figure 31-264. atmega168pa: reset input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) 105c 8 5c 25c -40c 0.25 0. 3 0. 3 5 0.4 0.45 0.5 0.55 0.6 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (v) 105c 8 5c 25c -40c 0.6 0.7 0. 8 0. 9 1 1.1 1.2 1. 3 1.4 1.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 465 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-265. atmega168pa: reset input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 31-266. atmega168pa: reset pin input hysteresis vs. v cc 105c 8 5c 25c -40c 0.5 0.7 0. 9 1.1 1. 3 1.5 1.7 1. 9 2.1 2. 3 2.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 105c 8 5c 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) inp u t hysteresis ( v ) 466 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.6.10 bod threshold figure 31-267. atmega168pa: bod thresholds vs. temperature (bodlevel is 1.8v) figure 31-268. atmega168pa: bod thresholds vs. temperature (bodlevel is 2.7v) ri s ing vcc f a lling vcc 1.76 1.77 1.7 8 1.7 9 1. 8 1. 8 1 1. 8 2 1. 83 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) thre s hold (v) f a lling vcc ri s ing vcc 2.62 2.64 2.66 2.6 8 2.7 2.72 2.74 2.76 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) thre s hold (v) 467 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-269. atmega168pa: bod thresholds vs. temperature (bodlevel is 4.3v) figure 31-270. atmega168pa: calibrated bandgap voltage vs. temperature ri s ing vcc f a lling vcc 4.2 4.22 4.24 4.26 4.2 8 4. 3 4. 3 2 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) thre s hold (v) 5.5v 4.5v 4.0v 3 . 3 v 2.7v 1. 8 v 1.116 1.11 8 1.12 1.122 1.124 1.126 1.12 8 1.1 3 1.1 3 2 1.1 3 4 1.1 3 6 -50 - 3 0-10 10 3 05070 9 0110 temper a t u re (c) b a ndg a p volt a ge (v) 468 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-271. atmega168pa: calibrated bandgap voltage vs. vcc 31.6.11 internal oscillator speed figure 31-272. atmega168pa: watchdog oscillator frequency vs. temperature 105c 8 5c 25c -40c 1.116 1.11 8 1.12 1.122 1.124 1.126 1.12 8 1.1 3 1.1 3 2 1.1 3 4 1.1 3 6 1.5 2 2.5 33 .5 4 4.5 5 5.5 vcc (v) b a ndg a p volt a ge (v) 5.5v 5.0v 4.5v 4.0v 3 . 3 v 2.7v 10 8 110 112 114 116 11 8 120 122 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0100 temper a t u re (c) f rc (khz) 469 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-273. atmega168pa: watchdog os cillator frequency vs. v cc figure 31-274. atmega168pa: calibrated 8mhz rc oscillator frequency vs. v cc 105c 8 5c 25c -40c 10 8 110 112 114 116 11 8 120 122 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) f rc (khz) 105c 8 5c 25c -40c 7.5 7.6 7.7 7. 8 7. 9 8 8 .1 8 .2 8 . 3 8 .4 8 .5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) f rc (mhz) 470 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-275. atmega168pa: calibrated 8mhz rc o scillator frequency vs. temperature figure 31-276. atmega168pa: calibrated 8mhz rc o scillator frequency vs. osccal value 5.5v 4.5v 4.0v 3 . 3 v 1. 8 v 7.5 7.6 7.7 7. 8 7. 9 8 8 .1 8 .2 8 . 3 8 .4 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) f rc (mhz) 105c 8 5c 25c -40c 2 4 6 8 10 12 14 016 3 24 8 64 8 0 9 611212 8 144 160 176 1 9 220 8 224 240 256 o s ccal (x1) f rc (mhz) 471 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.6.12 current consumption of peripheral units figure 31-277. atmega168pa: adc current vs. v cc (aref = av cc ) figure 31-278. atmega168pa: analog comparator current vs. v cc 105c 8 5c 25c -40c 100 125 150 175 200 225 250 275 3 00 3 25 1.5 2 2.5 33 .544.555.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 3 0 40 50 60 70 8 0 9 0 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 472 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-279. atmega168pa: aref external reference current vs. v cc figure 31-280. atmega168pa: brownout detector current vs. v cc 105c 8 5c 25c -40c 40 60 8 0 100 120 140 160 1 8 0 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 14 16 1 8 20 22 24 26 2 8 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 473 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-281. atmega168pa: programming current vs. v cc 31.6.13 current consumption in reset and reset pulsewidth figure 31-282. atmega168pa: reset supply current vs. low frequency (0.1mhz - 1.0mhz) 105c 8 5c 25c -40c 1 2 3 4 5 6 7 8 9 1.5 2 2.5 33 .544.555.5 v cc (v) i cc (ma) 5.5v 4.5v 4.0v 3 . 3 v 2.7v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 474 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-283. atmega168pa: reset supply current vs. frequency (1mhz - 20mhz) figure 31-284. atmega168pa: minimum rese t pulse width vs. vcc 5.5v 5.0v 4.5v 0 0. 3 0.6 0. 9 1.2 1.5 1. 8 2.1 2.4 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7v 3 .6v 4.0v 105c 8 5c 25c -40c 0 200 400 600 8 00 1000 1200 1400 1600 1 8 00 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) p u l s ewidth (n s ) 475 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.7 atmega328 typical characteristics 31.7.1 active supply current figure 31-285. atmega328: active supply current vs. low frequency (0.1-1.0mhz) figure 31-286. atmega328: active supply current vs. frequency (1-20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.2 0.4 0.6 0. 8 1 1.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 2 4 6 8 10 12 14 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 3.3 v 4.0 v 476 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-287. atmega328: active supply current vs. v cc (internal rc oscillator, 128khz) figure 31-288. atmega328: active supply current vs. v cc (internal rc oscillator, 1mhz) 8 5 c 25 c -40 c 0 0.04 0.0 8 0.12 0.16 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 477 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-289. atmega328: active supply current vs. v cc (internal rc oscillator, 8mhz) 31.7.2 idle supply current figure 31-290. atmega328: idle supply current vs. low frequency (0.1-1.0mhz) 8 5 c 25 c -40 c 0 1 2 3 4 5 6 7 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.04 0.0 8 0.12 0.16 0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 478 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-291. atmega328: idle supply current vs. frequency (1-20mhz) figure 31-292. atmega328: idle supply current vs. v cc (internal rc o scillator, 128khz) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 3 3.5 4 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 3.3 v 4.0 v 8 5 c 25 c -40 c 0 0.01 0.02 0.03 0.04 0.05 0.06 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 479 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-293. atmega328: idle supply current vs. v cc (internal rc o scillator, 1mhz) figure 31-294. atmega328: idle supply current vs. vcc (internal rc oscillator, 8mhz) 8 5 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 8 5 c 25 c -40 c 0 0.4 0. 8 1.2 1.6 2 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 480 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.7.3 atmega328 supply current of io modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules are controlled by the power reduc- tion register. see ?power reduction register? on page 41 for details. it is possible to calculate the typical cu rrent consumption based on the numbers from table 31-13 for other v cc and frequency settings than listed in table 31-14 . 31.7.3.1 example calculate the expected current consumption in idle mode with timer1, adc, and spi enabled at v cc = 2.0v and f = 1mhz. from table 31-14 , third column, we see that we need to add 14.5% for the timer1, 22.1% for the adc, and 15.7% for the spi module. reading from figure 31-338 on page 503 , we find that the idle current consumption is ~0.055 ma at v cc = 2.0v and f = 1mhz. the total current consumption in idle mode with timer1, adc, and spi enabled, gives: table 31-13. atmega328: additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz prusart0 3.20 a 22.17 a 100.25 a prtwi 7.34 a 46.55 a 199.25 a prtim2 7.34 a 50.79 a 224.25 a prtim1 6.19 a 41.25 a 176.25 a prtim0 1.89 a 14.28 a 61.13 a prspi 6.94 a 43.84 a 186.50 a pradc 8.66 a 61.80 a 295.38 a table 31-14. atmega328: additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 31-332 on page 500 and figure 31-333 on page 500 ) additional current consumption compared to idle with external clock (see figure 31-337 on page 502 and figure 31-338 on page 503 ) prusart0 1.4% 7.8% prtwi 3.0% 16.6% prtim2 3.3% 17.8% prtim1 2.7% 14.5% prtim0 0.9% 4.8% prspi 2.9% 15.7% pradc 4.1% 22.1% i cc total 0.045 ma (1 + 0.145 + 0.221 + 0.157) ? 0.069 ma ?? 481 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.7.4 power-down supply current figure 31-295. atmega328: power-down supply current vs. v cc (watchdog timer disabled) figure 31-296. atmega328: power-down supply current vs. v cc (watchdog timer enabled) 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 8 5 c 25 c -40 c 0 1 2 3 4 5 6 7 8 9 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 482 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.7.5 power-save supply current figure 31-297. atmega328: power-save supply current vs. v cc (watchdog timer disabled and 32khz crystal oscillator running) 31.7.6 standby supply current figure 31-298. atmega328: standby supply current vs. vcc (watchdog timer disabled) 25 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 2mhz_xtal 2mhz_res 1mhz_res 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 483 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.7.7 pin pull-up figure 31-299. atmega328: i/o pin pull-up resistor current vs. input voltage (v cc = 1.8 v) figure 31-300. atmega328: i/o pin pull-up resistor current vs. input voltage (v cc = 2.7 v) 8 5 c 25 c -40 c 0 10 20 30 40 50 60 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 v op ( v ) i op ( u a) 8 5 c 25 c -40 c 0 10 20 30 40 50 60 70 8 0 90 0 0.5 1 1.5 2 2.5 3 v op ( v ) i op ( u a) 484 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-301. atmega328: i/o pin pull-up resistor current vs. input voltage (v cc = 5 v) figure 31-302. atmega328: reset pull-up resistor current vs. reset pin voltage (v cc =1.8v) 0 20 40 60 8 0 100 120 140 160 0123456 v op ( v ) i op ( u a) 8 5 c 25 c -40 c 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 v reset ( v ) i reset ( u a) 8 5 c 25 c -40 c 485 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-303. atmega328: reset pull-up resistor current vs. reset pin voltage (v cc =2.7v) figure 31-304. atmega328: reset pull-up resistor current vs. reset pin voltage (v cc = 5 v) 0 10 20 30 40 50 60 70 0 0.5 1 1.5 2 2.5 3 v reset ( v ) i reset ( u a) 8 5 c 25 c -40 c 0 20 40 60 8 0 100 120 012 3 456 v re s et (v) i re s et ( u a) 8 5 c 25 c -40 c 486 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.7.8 pin driver strength figure 31-305. atmega328: i/o pin output voltage vs. sink current (v cc = 3 v) figure 31-306. atmega328: i/o pin output voltage vs. sink current (v cc = 5 v) 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 0 5 10 15 20 25 i ol (ma) v ol ( v ) 8 5 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0 5 10 15 20 25 i ol (ma) v ol ( v ) 487 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-307. atmega328: i/o pin output voltage vs. source current (vcc = 3 v) figure 31-308. atmega328: i/o pin output voltage vs. source current (v cc = 5 v) 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 3.5 0 5 10 15 20 25 i oh (ma) v oh ( v ) i/o pi n output v oltage v s. source curre n t v cc = 5 v 8 5 c 25 c -40 c 4.3 4.4 4.5 4.6 4.7 4. 8 4.9 5 5.1 0 5 10 15 20 25 i oh (ma) v oh ( v ) 488 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.7.9 pin threshold and hysteresis figure 31-309. atmega328: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 31-310. atmega328: i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0?) 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 3.5 4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) i/o pi n i n put threshold v oltage v s. v cc v il, io pi n read as ' 0 ' 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 489 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-311. atmega328: i/o pin input hysteresis vs. v cc figure 31-312. atmega328: reset input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) i/o pin input hy s tere s i s v s . v cc 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (v) 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 490 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-313. atmega328: reset input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 31-314. atmega328: reset pin input hysteresis vs. v cc 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) threshold ( v ) 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (v) 491 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.7.10 bod threshold figure 31-315. atmega328: bod thresholds vs. te mperature (bodl evel is 1.8 v) figure 31-316. atmega328: bod thresholds vs. te mperature (bodl evel is 2.7 v) 1 0 1.75 1.77 1.79 1. 8 1 1. 8 3 1. 8 5 -60 -40 -20 0 20 40 60 8 0 100 temperat u re (c) threshold ( v ) 1 0 2.66 2.6 8 2.7 2.72 2.74 2.76 2.7 8 -60 -40 -20 0 20 40 60 8 0100 temperat u re (c) threshold ( v ) 492 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-317. atmega328: bod thresholds vs. te mperature (bodl evel is 4.3 v) figure 31-318. atmega328: bandgap voltage vs. v cc 1 0 4.25 4.3 4.35 4.4 -60 -40 -20 0 20 40 60 8 0 100 temperat u re (c) threshold ( v ) 8 5 c 25 c -40 c 1.124 1.126 1.12 8 1.13 1.132 1.134 1.136 1.13 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) bandgap v oltage ( v ) 493 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.7.11 internal oscillator speed figure 31-319. atmega328: watchdog oscillator frequency vs. temperature figure 31-320. atmega328: watchdog osc illator frequency vs. v cc 5.5 v 4.0 v 3.3 v 2.7 v 109 110 111 112 113 114 115 116 117 11 8 119 -60 -40 -20 0 20 40 60 8 0100 temperat u re (c) f rc (khz) 8 5 c 25 c -40 c 1.5 2 2.5 3 3.5 4 4.5 5 5.5 ( v ) f rc (khz) 10 8 110 112 114 116 11 8 120 v cc 494 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-321. atmega328: calibrated 8mhz rc oscillator frequency vs. v cc figure 31-322. atmega328: calibrated 8mhz rc osc illator frequency vs . temperature calibrated 8 mhz rc o s cillator frequency v s . v cc 8 5 c 25 c -40 c 7.4 7.6 7. 8 8 8 .2 8 .4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) f rc (mhz) 5.0 v 3.0 v 7.6 7.7 7. 8 7.9 8 8 .1 8 .2 8 .3 8 .4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090100 temperat u re (c) f rc (mhz) 495 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-323. atmega328: calibrated 8mhz rc osc illator frequency vs. osccal value 31.7.12 current consumption of peripheral units figure 31-324. atmega328: adc current vs. v cc (aref = av cc ) 8 5 c 25 c -40 c 0 2 4 6 8 10 12 14 16 016 3 24 8 64 8 0 9 6 112 12 8 144 160 176 1 9 220 8 224 240 256 o s ccal (x1) f rc (mhz) 8 5 c 25 c -40 c 0 50 100 150 200 250 300 350 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc ( u a) 496 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-325. atmega328: analog comparator current vs. v cc figure 31-326. atmega328: aref external reference current vs. v cc 8 5 c 25 c -40 c 0 20 40 60 8 0 100 120 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) 8 5 c 25 c -40 c 0 20 40 60 8 0 100 120 140 160 1 8 0 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) 497 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-327. atmega328: brownout detector current vs. v cc figure 31-328. atmega328: programming current vs. v cc 8 5 c 25 c -40 c 0 5 10 15 20 25 3 0 1.5 2 2.5 33 .544.555.5 v cc (v) i cc ( u a) 8 5 c 25 c -40 c 0 1 2 3 4 5 6 7 8 9 10 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 498 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.7.13 current consumption in reset and reset pulsewidth figure 31-329. atmega328: reset supply current vs. low frequency (0.1 - 1.0mhz) figure 31-330. atmega328: reset supply current vs. frequency (1 - 20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1. 8 v 0 0.05 0.1 0.15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 3 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 3.3 v 4.0 v 499 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-331. atmega328: minimum reset pulse width vs. v cc 8 5 c 25 c -40 c 0 200 400 600 8 00 1000 1200 1400 1600 1 8 00 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) p u l s ewidth (n s ) 500 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.8 atmega328p typical characteristics 31.8.1 active supply current figure 31-332. atmega328p: active supply current vs. low frequency (0.1-1.0mhz) figure 31-333. atmega328p: active supply current vs. frequency (1-20mhz) 5.5v 5.0v 4.5v 4.0v 3 .6v 2.7v 1. 8 v 0 0.2 0.4 0.6 0. 8 1 1.2 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 5.5v 5.0v 4.5v 0 0.5 1 1.5 2 2.5 3 3 .5 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7v 3 .6v 4.0v 501 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-334. atmega328p: active supply current vs. v cc (internal rc osc illator, 128khz) figure 31-335. atmega328p: active supply current vs. v cc (internal rc os cillator, 1mhz) 105c 8 5c 25c -40c 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 502 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-336. atmega328p: active supply current vs. v cc (internal rc os cillator, 8mhz) 31.8.2 idle supply current figure 31-337. atmega328p: idle supply current vs. low frequency (0.1-1.0mhz) 105c 8 5c 25c -40c 1 2 3 4 5 6 7 1.522.5 33 .544.555.5 v cc (v) i cc (ma) 5.5v 5.0v 4.5v 4.0v 3 .6v 2.7v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0.1 8 0.2 0 0.2 0.4 0.6 0. 8 1 fre qu ency (mhz) i cc (ma) 503 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-338. atmega328p: idle supply current vs. frequency (1-20mhz) figure 31-339. atmega328p: idle supply current vs. v cc (internal rc osc illator, 128khz) 5.5v 5.0v 4.5v 0 0.5 1 1.5 2 2.5 3 3 .5 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7v 3 .6v 4.0v 105c 8 5c 25c -40c 0.005 0.01 0.015 0.02 0.025 0.0 3 0.0 3 5 0.04 0.045 0.05 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 504 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-340. atmega328p: idle supply current vs. v cc (internal rc oscillator, 1mhz) figure 31-341. atmega328p idle supply current vs. vcc (internal rc os cillator, 8mhz) 105c 8 5c 25c -40c 0.1 0.15 0.2 0.25 0. 3 0. 3 5 0.4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 505 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.8.3 atmega328p supply current of io modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules are controlled by the power reduc- tion register. see ?power reduction register? on page 41 for details. it is possible to calculate the typical cu rrent consumption based on the numbers from table 31-15 for other v cc and frequency settings than listed in table 31-16 . 31.8.3.1 example calculate the expected current consumption in idle mode with timer1, adc, and spi enabled at v cc = 2.0v and f = 1mhz. from table 31-16 , third column, we see that we need to add 14.5% for the timer1, 22.1% for the adc, and 15.7% for the spi module. reading from figure 31-338 on page 503 , we find that the idle current consumption is ~0.055 ma at v cc = 2.0v and f = 1mhz. the total current consumption in idle mode with timer1, adc, and spi enabled, gives: table 31-15. atmega328p: additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz prusart0 3.20 a 22.17 a 100.25 a prtwi 7.34 a 46.55 a 199.25 a prtim2 7.34 a 50.79 a 224.25 a prtim1 6.19 a 41.25 a 176.25 a prtim0 1.89 a 14.28 a 61.13 a prspi 6.94 a 43.84 a 186.50 a pradc 8.66 a 61.80 a 295.38 a table 31-16. atmega328p: additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 31-332 on page 500 and figure 31-333 on page 500 ) additional current consumption compared to idle with external clock (see figure 31-337 on page 502 and figure 31-338 on page 503 ) prusart0 1.4% 7.8% prtwi 3.0% 16.6% prtim2 3.3% 17.8% prtim1 2.7% 14.5% prtim0 0.9% 4.8% prspi 2.9% 15.7% pradc 4.1% 22.1% i cc total 0.045 ma (1 + 0.145 + 0.221 + 0.157) ? 0.069 ma ?? 506 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.8.4 power-down supply current figure 31-342. atmega328p: power-down supply current vs. v cc (watchdog timer disabled) figure 31-343. atmega328p: power-down supply current vs. v cc (watchdog timer enabled) 105c 8 5c 25c -40c 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 2 3 4 5 6 7 8 9 10 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 507 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.8.5 power-save supply current figure 31-344. atmega328p: power-save supply current vs. v cc (watchdog timer disabled and 32khz crystal oscillator running) 31.8.6 standby supply current figure 31-345. atmega328p: standby supply current vs. vcc (watchdog timer disabled) 105c 8 5c 25c -40c 0 0.5 1 1.5 2 2.5 3 3 .5 4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 2mhz_xtal 2mhz_res 1mhz_res 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 508 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.8.7 pin pull-up figure 31-346. atmega328p: i/o pin pull-up resistor current vs. input voltage (v cc = 1.8v) figure 31-347. atmega328p: i/o pin pull-up resistor current vs. input voltage (v cc = 2.7v) 105c 8 5c 25c -40c 0 5 10 15 20 25 30 35 40 45 50 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 v op ( v ) i op ( a) 105c 8 5c 25c -40c 0 10 20 3 0 40 50 60 70 8 0 0 0.5 1 1.5 2 2.5 3 v op (v) i op (a) 509 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-348. atmega328p: i/o pin pull-up resistor current vs. input voltage (v cc = 5v) figure 31-349. atmega328p: reset pull-up resistor current vs. reset pin voltage (v cc = 1.8v) 0 20 40 60 8 0 100 120 140 160 012 3 45 v op (v) i op (a) 105c 8 5c 25c -40c 105c 8 5c 25c -40c 0 5 10 15 20 25 3 0 3 5 40 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v re s et (v) i re s et (a) 510 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-350. atmega328p: reset pull-up resistor current vs. reset pin voltage (v cc = 2.7v) figure 31-351. atmega328p: reset pull-up resistor current vs. reset pin voltage (v cc = 5v) 0 10 20 3 0 40 50 60 00. 3 0.6 0. 9 1.2 1.5 1. 8 2.1 2.4 2.7 v re s et (v) i re s et (a) 105c 8 5c 25c -40c 0 20 40 60 8 0 100 120 0 0.5 1 1.5 2 2.5 33 .5 4 4.5 5 v re s et (v) i re s et (a) 105c 8 5c 25c -40c 511 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.8.8 pin driver strength figure 31-352. atmega328p: i/o pin output voltage vs. sink current (v cc = 3v) figure 31-353. atmega328p: i/o pin output voltage vs. sink current (v cc = 5v) 105c 8 5c 25c -40c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 0 5 10 15 20 i ol (ma) v ol (v) 105c 8 5c 25c -40c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0 5 10 15 20 i ol (ma) v ol (v) 512 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-354. atmega328p: i/o pin output voltage vs. source current (vcc = 3v) figure 31-355. atmega328p: i/o pin output voltage vs. source current (v cc = 5v) 105c 8 5c 25c -40c 1. 9 2.1 2. 3 2.5 2.7 2. 9 3 .1 0 5 10 15 20 i oh (ma) v oh (v) 105c 8 5c 25c -40c 4. 3 4.4 4.5 4.6 4.7 4. 8 4. 9 5 5.1 0 5 10 15 20 i oh (ma) v oh (v) 513 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.8.9 pin threshold and hysteresis figure 31-356. atmega328p: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 31-357. atmega328p: i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0? 105c 8 5c 25c -40c 1 1. 3 1.6 1. 9 2.2 2.5 2. 8 3 .1 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 105c 8 5c 25c -40c 0.2 0.5 0. 8 1.1 1.4 1.7 2 2. 3 2.6 1.5 2 2.5 33 .544.555.5 v cc (v) thre s hold (v) 514 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-358. atmega328p: i/o pin input hysteresis vs. v cc figure 31-359. atmega328p: reset input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) 105c 8 5c 25c -40c 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 1. 8 2. 3 2. 83 . 33 . 8 4. 3 4. 8 5. 3 v cc (v) inp u t hy s tere s i s (mv) 105c 8 5c 25c -40c 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 2.6 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 515 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-360. atmega328p: reset input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 31-361. atmega328p: reset pin input hysteresis vs. v cc 105c 8 5c 25c -40c 0.5 0.7 0. 9 1.1 1. 3 1.5 1.7 1. 9 2.1 2. 3 2.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 105c 8 5c 25c -40c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (v) 516 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.8.10 bod threshold figure 31-362. atmega328p: bod thresholds vs. te mperature (bodlevel is 1.8v) figure 31-363. atmega328p bod thresholds vs. te mperature (bodlevel is 2.7v) ri s ing vcc f a lling vcc 1.7 8 1.7 9 1. 8 1. 8 1 1. 8 2 1. 83 1. 8 4 -50 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) thre s hold (v) ri s ing vcc f a lling vcc 2.66 2.67 2.6 8 2.6 9 2.7 2.71 2.72 2.7 3 2.74 2.75 2.76 2.77 2.7 8 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) thre s hold (v) 517 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-364. atmega328p bod thresholds vs. te mperature (bodlevel is 4.3v) figure 31-365. atmega328p: calibrated bandgap voltage vs. vcc ri s ing vcc f a lling vcc 4.24 4.26 4.2 8 4. 3 4. 3 2 4. 3 4 4. 3 6 4. 38 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) thre s hold (v) 105c 8 5c 25c -40c 1.121 1.124 1.127 1.1 3 1.1 33 1.1 3 6 1.1 39 1.5 2 2.5 33 .5 4 4.5 5 5.5 vcc (v) b a ndg a p volt a ge (v) 518 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.8.11 internal oscillator speed figure 31-366. atmega328p: watchdog oscillato r frequency vs . temperature figure 31-367. atmega328p ? c watchdog oscillator frequency vs. v cc 5.5v 4.0v 3 .6v 2.7v 106 10 8 110 112 114 116 11 8 120 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) f rc (khz) 105c 8 5c 25c -40c 106 10 8 110 112 114 116 11 8 120 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) f rc (khz) 519 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-368. atmega328p: calibrated 8 mhz rc oscillator frequency vs. v cc figure 31-369. atmega328p: calibrated 8mhz rc osc illator frequency vs. temperature 105c 8 5c 25c -40c 7.4 7.6 7. 8 8 8 .2 8 .4 8 .6 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) f rc (mhz) 5.5v 5.0v 4.5v 4.0v 3 .6v 2.7v 1. 8 v 7.5 7.6 7.7 7. 8 7. 9 8 8 .1 8 .2 8 . 3 8 .4 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) f rc (mhz) 520 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-370. atmega328p calibrated 8mhz rc oscilla tor frequency vs . osccal value 31.8.12 current consumption of peripheral units figure 31-371. atmega328p: adc current vs. v cc (aref = av cc ) 105c 8 5c 25c -40c 4 5 6 7 8 9 10 11 12 1 3 14 016 3 24 8 64 8 0 9 6 112 12 8 144 160 176 1 9 220 8 224 240 o s ccal (x1) f rc (mhz) 105c 8 5c 25c -40c 40 60 8 0 100 120 140 160 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 521 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-372. atmega328p: analog comparator current vs. v cc figure 31-373. atmega328p: aref external reference current vs. v cc 105c 8 5c 25c -40c 3 0 40 50 60 70 8 0 9 0 100 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 40 60 8 0 100 120 140 160 1 8 0 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 522 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-374. atmega328p: brownout detector current vs. v cc figure 31-375. atmega328p: programming current vs. v cc 105c 8 5c 25c -40c 10 15 20 25 3 0 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 1 2 3 4 5 6 7 8 9 10 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 523 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.8.13 current consumption in reset and reset pulsewidth figure 31-376. atmega328p: reset supply current vs. low frequency (0.1mhz - 1.0mhz) figure 31-377. atmega328p reset supply current vs. frequency (1mhz - 20mhz) 5.5v 5.0v 4.5v 4.0v 3 .6v 2.7v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 5.5v 5.0v 4.5v 0 0.5 1 1.5 2 2.5 3 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 4.0v 3 .6v 2.7v 1. 8 v 524 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 31-378. atmega328p: minimum reset pulse width vs. vcc 105c 8 5c 25c -40c 0 200 400 600 8 00 1000 1200 1400 1600 1 8 00 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) p u l s ewidth (n s ) 525 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 32. atmega48pa typical characteristics ? (t a = -40c to 105c) the following charts show typical behavior. these figures ar e not tested during manufacturing. all current consumption measurements are performed with all i/o pins configured as inputs and with internal pull-ups enabled. a square wave generator with rail-to-rail output is used as clock source. all active- and idle current consumption measurements are d one with all bits in the prr register set and thus, the corresponding i/o modules are turned off. also the analog comparator is disabled during these measurements. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors su ch as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient temperature. the dominating factors are operating voltage and frequency. the current drawn from capacitive loaded pins may be estimated (for one pin) as c l * v cc *f where c l = load capacitance, v cc = operating voltage and f = average switching frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. the difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the di fferential current drawn by the watchdog timer. 32.1 active supply current figure 32-1. atmega48pa: active supply current vs. low frequency (0.1mhz -1.0mhz) 5.5v 5.0v 4.5v 4.0v 3 .6v 3 . 3 v 2.7v 1. 8 v 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 526 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 32-2. atmega48pa: active supply current vs. frequency (1mhz - 20mhz) figure 32-3. atmega48pa: active supply current vs. v cc (internal rc oscillator, 128khz) 5.5v 5.0v 4.5v 0 1 2 3 4 5 6 7 8 9 10 11 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 4.0v 3 . 3 v 2.7v 1. 8 v 105c 8 5c 25c -40c 0.024 0.0 3 42 0.0444 0.0546 0.064 8 0.075 0.0 8 52 0.0 9 54 0.1056 0.115 8 0.126 1. 8 2.17 2.54 2. 9 1 3 .2 83 .65 4.02 4. 39 4.76 5.1 3 5.5 v cc (v) i cc (ma) 527 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 32-4. atmega48pa: active supply current vs. v cc (internal rc oscillator, 1mhz) figure 32-5. atmega48pa: active supply current vs. v cc (internal rc oscillator, 8mhz) 105c 8 5c 25c -40c 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 1.1 1.2 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 0.5 1 1.5 2 2.5 3 3 .5 4 4.5 5 5.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 528 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 32.2 idle supply current figure 32-6. atmega48pa: idle supply cu rrent vs. low frequency (0.1mhz -1.0mhz) figure 32-7. atmega48pa: idle supply current vs. frequency (1mhz - 20mhz) 5.5v 5.0v 4.5v 4.0v 3 . 3 v 2.7v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 5.5v 5.0v 4.5v 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 2.6 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 4.0v 3 . 3 v 2.7v 1. 8 v 529 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 32-8. atmega48pa: idle supply current vs. v cc (internal rc oscillator, 128khz) figure 32-9. atmega48pa: idle supply current vs. v cc (internal rc oscillator, 1mhz) 105c 8 5c 25c -40c 0.005 0.01 0.015 0.02 0.025 0.0 3 0.0 3 5 0.04 0.045 0.05 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 0.0 8 0.1 3 0.1 8 0.2 3 0.2 8 0. 33 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 530 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 32-10.atmega48pa: idle supply curre nt vs. vcc (internal rc oscillator, 8mhz) 32.3 power-down supply current figure 32-11.atmega48pa: power-down supply current vs. v cc (watchdog timer disabled) 105c 8 5c 25c -40c 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 1.1 1.2 1. 3 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 0 0. 3 0.6 0. 9 1.2 1.5 1. 8 2.1 2.4 2.7 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 531 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 32-12.atmega48pa: power-down supply current vs. v cc (watchdog timer enabled) 32.4 power-save supply current figure 32-13.atmega48pa: power-save supply current vs. v cc (watchdog timer disabled and 32khz crystal oscilla- tor running) 105c 8 5c 25c -40c 2.5 3 3 .5 4 4.5 5 5.5 6 6.5 7 7.5 8 8 .5 9 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 532 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 32.5 standby supply current figure 32-14.atmega48pa: standby supply current vs. vcc (watchdog timer disabled) 32.6 pin pull-up figure 32-15.atmega48pa: i/o pin pull-u p resistor current vs. input voltage (v cc = 1.8v) 6mhz_xt a l 6mhz_re s 4mhz_xt a l 4mhz_re s 450khz_re s 2mhz_xt a l 2mhz_re s 1mhz_re s 0.0 15 3 0 45 60 75 9 0 105 120 1 3 5 150 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 0 5 10 15 20 25 3 0 3 5 40 45 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v op (v) i op (a) 533 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 32-16.atmega48pa: i/o pin pull-u p resistor current vs. input voltage (v cc = 2.7v) figure 32-17.atmega48pa: i/o pin pull-u p resistor current vs. input voltage (v cc = 5v) 0 10 20 3 0 40 50 60 70 00. 3 0.6 0. 9 1.2 1.5 1. 8 2.1 2.4 2.7 v op (v) i op (a) 105c -40c 25c 8 5c 105c 8 5c 25c -40c 0 15 3 0 45 60 75 9 0 105 120 00.511.522.5 33 .5 4 4.5 5 v op (v) i op (a) 534 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 32-18.atmega48pa: reset pull-up re sistor current vs. reset pin voltage (v cc = 1.8v) figure 32-19.atmega48pa: reset pull-up re sistor current vs. reset pin voltage (v cc = 2.7v) 105c 8 5c 25c -40c 0 5 10 15 20 25 3 0 3 5 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v re s et (v) i re s et (a) 0 4 8 12 16 20 24 2 8 3 2 3 6 40 44 4 8 52 00. 3 0.6 0. 9 1.2 1.5 1. 8 2.1 2.4 2.7 v re s et (v) i re s et (a) 105c 8 5c 25c -40c 535 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 32-20.atmega48pa: reset pull-up re sistor current vs. reset pin voltage (v cc = 5v) 32.7 pin driver strength figure 32-21.atmega48pa: i/o pin ou tput voltage vs. sink current (v cc = 3v) 105c 8 5c 25c -40c 0 10 20 3 0 40 50 60 70 8 0 9 0 100 110 00.511.522.5 33 .5 4 4.5 5 v re s et (v) i re s et (a) 105c 8 5c 25c -40c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol (v) 536 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 32-22.atmega48pa: i/o pin ou tput voltage vs. sink current (v cc = 5v) figure 32-23.atmega48pa: i/o pin output voltage vs. source current (vcc = 3v) 105c 8 5c 25c -40c 0 0.05 0.1 0.15 0.2 0.25 0. 3 0. 3 5 0.4 0.45 0.5 0.55 0.6 0.65 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol (v) 105c 8 5c 25c -40c 1. 9 2 2.1 2.2 2. 3 2.4 2.5 2.6 2.7 2. 8 2. 9 3 0246 8 10 12 14 16 1 8 20 i oh (ma) v oh (v) 537 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 32-24.atmega48pa: i/o pin output voltage vs. source current (v cc = 5v) 32.8 pin threshold and hysteresis figure 32-25.atmega48pa: i/o pi n input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) 105c 8 5c 25c -40c 4. 3 4.4 4.5 4.6 4.7 4. 8 4. 9 5 0246 8 10 12 14 16 1 8 20 i oh (ma) v oh (v) 105c 8 5c 25c -40c 0. 8 1.1 1.4 1.7 2 2. 3 2.6 2. 9 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 538 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 32-26.atmega48pa: i/o pi n input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 32-27.atmega48pa: i/o pin input hysteresis vs. v cc 105c 8 5c 25c -40c 0. 3 0.6 0. 9 1.2 1.5 1. 8 2.1 2.4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 105c 8 5c 25c -40c 0.25 0. 3 0. 3 5 0.4 0.45 0.5 0.55 0.6 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (mv) -40 c 105 c 8 5 c 25 c 539 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 32-28.atmega48pa: reset input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 32-29.atmega48pa: reset input threshold voltage vs. v cc (v il , i/o pin read as ?0?) 105c 8 5c 25c -40c 0. 9 5 1.2 1.45 1.7 1. 9 5 2.2 2.45 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 105c 8 5c 25c -40c 105c 8 5c 25c -40c 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 540 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 32-30.atmega48pa: reset pin input hysteresis vs. v cc 32.9 bod threshold figure 32-31.atmega48pa: bod thresholds vs. temperature (bodlevel is 1.8v) 105c 8 5c 25c -40c 0 0.05 0.1 0.15 0.2 0.25 0. 3 0. 3 5 0.4 0.45 0.5 0.55 0.6 0.65 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (mv) -40c 25c 105c 8 5c ri s ing vcc f a lling vcc 1.765 1.77 1.775 1.7 8 1.7 8 5 1.7 9 1.7 9 5 1. 8 1. 8 05 1. 8 1 1. 8 15 1. 8 2 1. 8 25 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) thre s hold (v) 541 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 32-32.atmega48pa: bod thresholds vs. temperature (bodlevel is 2.7v) figure 32-33.atmega48pa: bod thresholds vs. temperature (bodlevel is 4.3v) 2.64 2.65 2.66 2.67 2.6 8 2.6 9 2.7 2.71 2.72 2.7 3 2.74 2.75 2.76 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) thre s hold (v) ri s ing vcc f a lling vcc ri s ing vcc f a lling vcc 4.2 4.22 4.24 4.26 4.2 8 4. 3 4. 3 2 4. 3 4 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) thre s hold (v) 542 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 32.10 internal oscilllator speed figure 32-34.atmega48pa: watchdog os cillator frequency vs. temperature figure 32-35.atmega48pa: watchd og oscillator frequency vs. v cc 5.5v 4.0v 3 . 3 v 2.7v 104 106 10 8 110 112 114 116 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) f rc (khz) 105c 8 5c 25c -40c 104 106 10 8 110 112 114 116 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) f rc (khz) 543 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 32-36.atmega48pa: calibrated 8mhz rc osci llator frequency vs. v cc figure 32-37.atmega48pa: ca librated 8mhz rc oscillator frequency vs. temperature 105c 8 5c 25c -40c 7.65 7.7 7.75 7. 8 7. 8 5 7. 9 7. 9 5 8 8 .05 8 .1 8 .15 8 .2 8 .25 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) f rc (mhz) 5.5v 4.0v 3 .0v 1. 8 v 7.65 7.7 7.75 7. 8 7. 8 5 7. 9 7. 9 5 8 8 .05 8 .1 8 .15 8 .2 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) f rc (mhz) 544 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 32-38.atmega48pa: ca librated 8mhz rc oscillator frequency vs. osccal value 32.11 current consumpti on of peripheral units figure 32-39.atmega48pa: adc current vs. v cc (aref = av cc ) 105c 8 5c 25c -40c 4 5 6 7 8 9 10 11 12 1 3 14 15 016 3 24 8 64 8 0 9 611212 8 144 160 176 1 9 220 8 224 240 256 o s ccal (x1) f rc (mhz) 105c 8 5c 25c -40c 1 3 0 150 170 1 9 0 210 2 3 0 250 270 2 9 0 3 10 1.5 2 2.5 33 .544.555.5 v cc (v) i cc (a) 545 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 32-40.atmega48pa: anal og comparator current vs. v cc figure 32-41.atmega48pa: aref ex ternal reference current vs. v cc 105c 8 5c 25c -40c 3 5 40 45 50 55 60 65 70 75 8 0 8 5 9 0 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) -40c 25c 8 5c 105c 105c 8 5c 25c -40c 40 50 60 70 8 0 9 0 100 110 120 1 3 0 140 150 1.5 2 2.5 33 .544.555.5 v cc (v) i cc (a) 546 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 32-42.atmega48pa: brownout detector current vs. v cc figure 32-43.atmega48pa: programming current vs. v cc 105c 8 5c 25c -40c 15 16 17 1 8 1 9 20 21 22 2 3 24 25 26 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 1 1.5 2 2.5 3 3 .5 4 4.5 5 5.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 547 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 32.12 current consumption in reset and reset pulsewidth figure 32-44.atmega48pa: reset supply cu rrent vs. low frequency (0.1mhz- 1.0mhz) figure 32-45.atmega48pa: reset supply current vs. frequency (1mhz- 20mhz) 5.5v 5.0v 4.5v 4.0v 3 . 3 v 2.7v 1. 8 v 0 0.01 0.02 0.0 3 0.04 0.05 0.06 0.07 0.0 8 0.0 9 0.1 0.11 0.12 0.1 3 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 5.5v 5.0v 4.5v 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7v 3 . 3 v 4.0v 548 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 32-46.atmega48pa: mini mum reset pulse width vs. v cc 105c 8 5c 25c -40c 200 3 00 400 500 600 700 8 00 9 00 1000 1100 1200 1 3 00 1400 1500 1600 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) p u l s ewidth (n s ) 549 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 33. atmega88pa typical characteristics ? (t a = -40c to 105c) the following charts show typical behavior. these figures ar e not tested during manufacturing. all current consumption measurements are performed with all i/o pins configured as inputs and with internal pull-ups enabled. a square wave generator with rail-to-rail output is used as clock source. all active- and idle current consumption measurements are d one with all bits in the prr register set and thus, the corresponding i/o modules are turned off. also the analog comparator is disabled during these measurements. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors su ch as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient temperature. the dominating factors are operating voltage and frequency. the current drawn from capacitive loaded pins may be estimated (for one pin) as c l * v cc *f where c l = load capacitance, v cc = operating voltage and f = average switching frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. the difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the di fferential current drawn by the watchdog timer. 33.1 active supply current figure 33-1. atmega88pa: active supply current vs. low frequency (0.1mhz -1.0mhz) 5.5v 5.0v 4.5v 4.0v 3 . 3 v 2.7v 1. 8 v 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 550 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 33-2. atmega88pa: active supply current vs. frequency (1mhz - 20mhz) figure 33-3. atmega88pa: active supply current vs. v cc (internal rc oscillator, 128khz) 5.5v 5.0v 4.5v 0 2 4 6 8 10 12 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 4.0v 3 . 3 v 2.7v 1. 8 v 105c 8 5c 25c -40c 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 551 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 33-4. atmega88pa: active supply current vs. v cc (internal rc oscillator, 1mhz) figure 33-5. atmega88pa: active supply current vs. v cc (internal rc oscillator, 8mhz) 105c 8 5c 25c -40c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 0 1 2 3 4 5 6 1.5 2 2.5 33 .544.555.5 v cc (v) i cc (ma) 552 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 33.2 idle supply current figure 33-6. atmega88pa: idle supply cu rrent vs. low frequency (0.1mhz -1.0mhz) figure 33-7. atmega88pa: idle supply current vs. frequency (1mhz - 20mhz) 5.5v 5.0v 4.5v 4.0v 3 . 3 v 2.7v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 5.5v 5.0v 4.5v 0 0.5 1 1.5 2 2.5 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 4.0v 3 . 3 v 2.7v 1. 8 v 553 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 33-8. atmega88pa: idle supply current vs. v cc (internal rc oscillator, 128khz) figure 33-9. atmega88pa: idle supply current vs. v cc (internal rc oscillator, 1mhz) 105c 8 5c 25c -40c 0 0.005 0.01 0.015 0.02 0.025 0.0 3 0.0 3 5 0.04 0.045 0.05 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 0 0.05 0.1 0.15 0.2 0.25 0. 3 0. 3 5 0.4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 554 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 33-10.atmega88pa: idle supply current vs. v cc (internal rc oscillator, 8mhz) 33.3 power-down supply current figure 33-11.atmega88pa: power-down supply current vs. v cc (watchdog timer disabled) 105c 8 5c 25c -40c 0 0.2 0.4 0.6 0. 8 1 1.2 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 0 1 2 3 4 5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 555 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 33-12.atmega88pa: power-down supply current vs. v cc (watchdog timer enabled) 33.4 power-save supply current figure 33-13.atmega88pa: power-save supply current vs. v cc (watchdog timer disabled and 32khz crystal oscilla- tor running) 105c 8 5c 25c -40c 0 2 4 6 8 10 12 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 0 2 4 6 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 556 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 33.5 pin pull-up figure 33-14.atmega88pa: i/o pin pull-u p resistor current vs. input voltage (v cc = 1.8v) figure 33-15.atmega88pa: i/o pin pull-u p resistor current vs. input voltage (v cc = 2.7v) 105c 8 5c 25c -40c 0 10 20 3 0 40 50 60 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 v op (v) i op (a) 105c 8 5c 25c -40c 0 10 20 3 0 40 50 60 70 8 0 0 0.5 1 1.5 2 2.5 3 v op (v) i op (a) 557 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 33-16.atmega88pa: i/o pin pull-u p resistor current vs. input voltage (v cc = 5v) figure 33-17.atmega88pa: reset pull-up re sistor current vs. reset pin voltage (v cc = 1.8v) 0 20 40 60 8 0 100 120 140 160 012 3 456 v op (v) i op (a) 105c 8 5c 25c -40c 105c 8 5c 25c -40c 0 5 10 15 20 25 3 0 3 5 40 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 v re s et (v) i re s et (a) 558 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 33-18.atmega88pa: reset pull-up re sistor current vs. reset pin voltage (v cc = 2.7v) figure 33-19.atmega88pa: reset pull-up re sistor current vs. reset pin voltage (v cc = 5v) 0 10 20 3 0 40 50 60 0 0.5 1 1.5 2 2.5 3 v re s et (v) i re s et (a) 105c 8 5c 25c -40c 0 20 40 60 8 0 100 120 012 3 456 v re s et (v) i re s et (a) 105c 8 5c 25c -40c 559 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 33.6 pin driver strength figure 33-20.atmega88pa: i/o pin ou tput voltage vs. sink current (v cc = 3v) figure 33-21.atmega88pa: i/o pin ou tput voltage vs. sink current (v cc = 5v) 105c 8 5c 25c -40c 0 0.2 0.4 0.6 0. 8 1 1.2 0 5 10 15 20 25 i ol (ma) v ol (v) 105c 8 5c 25c -40c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0 5 10 15 20 25 i ol (ma) v ol (v) 560 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 33-22.atmega88pa: i/o pin output voltage vs. source current (vcc = 3v) figure 33-23.atmega88pa: i/o pin output voltage vs. source current (v cc = 5v) 105c 8 5c 25c -40c 1.5 2 2.5 3 3 .5 0 5 10 15 20 25 i oh (ma) v oh (v) 105c 8 5c 25c -40c 4.2 4.4 4.6 4. 8 5 5.2 0 5 10 15 20 25 i oh (ma) v oh (v) 561 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 33.7 pin threshold and hysteresis figure 33-24.atmega88pa: i/o pi n input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 33-25.atmega88pa: i/o pi n input threshold voltage vs. v cc (v il , i/o pin read as ?0?) 105c 8 5c 25c -40c 0 0.5 1 1.5 2 2.5 3 3 .5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 105c 8 5c 25c -40c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 562 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 33-26.atmega88pa: i/o pin input hysteresis vs. v cc figure 33-27.atmega88pa: reset input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) 105c 8 5c 25c -40c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 1.5 2 2.5 33 .544.555.5 v cc (v) inp u t hy s tere s i s (mv) 105c 8 5c 25c -40c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 563 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 33-28.atmega88pa: reset input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 33-29.atmega88pa: reset pin input hysteresis vs. v cc 105c 8 5c 25c -40c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 105c 8 5c 25c -40c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (mv) 564 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 33.8 bod threshold figure 33-30.atmega88pa: bod thresholds vs. temperature (bodlevel is 1.8v) figure 33-31.atmega88pa: bod thresholds vs. temperature (bodlevel is 2.7v) ri s ing vcc f a lling vcc 1.76 1.77 1.7 8 1.7 9 1. 8 1. 8 1 1. 8 2 1. 83 1. 8 4 -60 -40 -20 0 20 40 60 8 0 100 120 temper a t u re (c) thre s hold (v) ri s ing vcc f a lling vcc 2.6 2.62 2.64 2.66 2.6 8 2.7 2.72 2.74 2.76 2.7 8 2. 8 -60 -40 -20 0 20 40 60 8 0 100 120 temper a t u re (c) thre s hold (v) 565 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 33-32.atmega88pa: bod thresholds vs. temperature (bodlevel is 4.3v) 33.9 internal oscilllator speed figure 33-33.atmega88pa: watchdog os cillator frequency vs. temperature ri s ing vcc f a lling vcc 4 4.05 4.1 4.15 4.2 4.25 4. 3 4. 3 5 4.4 4.45 4.5 -60 -40 -20 0 20 40 60 8 0100120 temper a t u re (c) thre s hold (v) 5.5v 4.0v 3 . 3 v 2.7v 102 104 106 10 8 110 112 114 116 -40 -20 0 20 40 60 8 0 100 120 temper a t u re (c) f rc (khz) 566 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 33-34.atmega88pa: watchd og oscillator frequency vs. v cc figure 33-35.atmega88pa: calibrated 8mhz rc osci llator frequency vs. v cc 105c 8 5c 25c -40c 102 104 106 10 8 110 112 114 116 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) f rc (khz) 105c 8 5c 25c -40c 7.5 7.75 8 8 .25 8 .5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) f rc (mhz) 567 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 33-36.atmega88pa: ca librated 8mhz rc oscillator frequency vs. temperature figure 33-37.atmega88pa: ca librated 8mhz rc oscillator frequency vs. osccal value 5.5v 4.0v 3 .0v 1. 8 v 7.6 7.7 7. 8 7. 9 8 8 .1 8 .2 8 . 3 8 .4 -60 -40 -20 0 20 40 60 8 0100120 temper a t u re (c) f rc (mhz) 105c 8 5c 25c -40c 0 2 4 6 8 10 12 14 016324 8 64 8 0 96 112 12 8 144 160 176 192 20 8 224 240 256 osccal (x1) f rc (mhz) 568 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 33.10 current consumpti on of peripheral units figure 33-38.atmega88pa: adc current vs. v cc (aref = av cc ) figure 33-39.atmega88pa: anal og comparator current vs. v cc 105c 8 5c 25c -40c 0 50 100 150 200 250 3 00 3 50 1.522.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 0 10 20 3 0 40 50 60 70 8 0 9 0 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 569 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 33-40.atmega88pa: aref ex ternal reference current vs. v cc figure 33-41.atmega88pa: brownout detector current vs. v cc 105c 8 5c 25c -40c 0 20 40 60 8 0 100 120 140 160 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 0 5 10 15 20 25 3 0 1.5 2 2.5 33 .544.555.5 v cc (v) i cc (a) 570 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 33-42.atmega88pa: programming current vs. v cc 33.11 current consumption in reset and reset pulsewidth figure 33-43.atmega88pa: reset supply cu rrent vs. low frequency (0.1mhz - 1.0mhz) 105c 8 5c 25c -40c 0 1 2 3 4 5 6 7 8 9 10 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 5.5v 5.0v 4.5v 4.0v 3 . 3 v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 571 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 33-44.atmega88pa: reset supply current vs. frequency (1mhz - 20mhz) figure 33-45.atmega88pa: mini mum reset pulse width vs. v cc 5.5v 5.0v 4.5v 0 0.5 1 1.5 2 2.5 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 4.0v 3 . 3 v 2.7v 1. 8 v 105c 8 5c 25c -40c 0 200 400 600 8 00 1000 1200 1400 1600 1 8 00 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) p u l s ewidth (n s ) 572 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 573 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 34. atmega168pa typical characteristics ? (t a = -40c to 105c) the following charts show typical behavior. these figures are not tested during manufacturing. all current con- sumption measurements are performed with all i/o pins conf igured as inputs and with internal pull-ups enabled. a sine wave generator with rail-to-rail output is used as clock source. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors such as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient temperature. the dominating factors are operating voltage and frequency. the current drawn from capacitive loaded pins may be estimated (for one pin) as c l * v cc *f where c l = load capac- itance, v cc = operating voltage and f = average switching frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. the difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the di fferential current drawn by the watchdog timer. 34.1 active supply current figure 34-1. atmega168pa: active supply current vs. low frequency (0.1mhz -1.0mhz) 5.5v 5.0v 4.5v 4.0v 3 . 3 v 2.7v 1. 8 v 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 574 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-2. atmega168pa: active supply current vs. frequency (1mhz - 20mhz) figure 34-3. atmega168pa: active supply current vs. v cc (internal rc oscillator, 128khz) 5.5v 5.0v 4.5v 0 2 4 6 8 10 12 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7v 3 .6v 4.0v 105c 8 5c 25c -40c 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 575 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-4. atmega168pa: active supply current vs. v cc (internal rc oscillator, 1mhz) figure 34-5. atmega168pa: active supply current vs. v cc (internal rc oscillator, 8mhz) 105c 8 5c 25c -40c 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 1.1 1.2 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 0.5 1 1.5 2 2.5 3 3 .5 4 4.5 5 5.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 576 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 34.2 idle supply current figure 34-6. atmega168pa: idle supply current vs. low frequency (0.1mhz - 1.0mhz) figure 34-7. atmega168pa: idle supply current vs. frequency (1mhz - 20mhz) 5.5v 5.0v 4.5v 4.0v 3 .6v 2.7v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 5.5v 5.0v 4.5v 0 0. 3 0.6 0. 9 1.2 1.5 1. 8 2.1 2.4 2.7 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7v 3 .6v 4.0v 577 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-8. atmega168pa: idle supply current vs. v cc (internal rc oscillator, 128khz) figure 34-9. atmega168pa: idle supply current vs. v cc (internal rc oscillator, 1mhz) 105c 8 5c 25c -40c 0.005 0.01 0.015 0.02 0.025 0.0 3 0.0 3 5 0.04 0.045 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 0.06 0.0 9 0.12 0.15 0.1 8 0.21 0.24 0.27 0. 3 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 578 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-10.atmega168pa: idle supply current vs. v cc (internal rc oscillator, 8mhz) 34.3 power-down supply current figure 34-11.atmega168pa: power-down supply current vs. v cc (watchdog timer disabled) 105c 8 5c 25c -40c 0.1 0. 3 0.5 0.7 0. 9 1.1 1. 3 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 0 0. 3 0.6 0. 9 1.2 1.5 1. 8 2.1 2.4 1.5 2 2.5 33 .544.555.5 v cc (v) i cc (a) 579 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-12.atmega168pa: powe r-down supply current vs. v cc (watchdog timer enabled) 34.4 power-save supply current figure 34-13.atmega168pa: power-save supply current vs. v cc (watchdog timer disabled and 32khz crystal oscilla- tor running) 105c 8 5c 25c -40c 3 4 5 6 7 8 9 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 0.5 1 1.5 2 2.5 3 3 .5 4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 580 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 34.5 standby supply current figure 34-14.atmega168pa: standby supply current vs. v cc (watchdog timer disabled). 34.6 pin pull-up figure 34-15.atmega168pa: i/o pin pull-up resistor current vs. input voltage (v cc = 1.8v) 6 mhz_xtal 6 mhz_res 4 mhz_xtal 4 mhz_res 2 mhz_xtal 2 mhz_res 1 mhz_res 0.02 0.03 0.04 0.05 0.06 0.07 0.0 8 0.09 0.1 0.11 0.12 0.13 0.14 0.15 22.533.544.555.5 v cc ( v ) i cc (ma) 105c 8 5c 25c -40c 0 5 10 15 20 25 3 0 3 5 40 45 50 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v op (v) i op (a) 581 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-16.atmega168pa: i/o pin pull-up resistor current vs. input voltage (v cc = 2.7v) figure 34-17.atmega168pa: i/o pin pull-up resistor current vs. input voltage (v cc = 5v) 105c 8 5c 25c -40c 0 10 20 3 0 40 50 60 70 8 0 0 0.5 1 1.5 2 2.5 3 v op (v) i op (a) 105c 8 5c 25c 0 20 40 60 8 0 100 120 140 012 3 45 v op (v) i op (a) -40c 582 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-18.atmega168pa: reset pull-up resistor current vs. reset pin voltage (v cc = 1.8v) figure 34-19.atmega168pa: reset pull-up resistor current vs. reset pin voltage (v cc = 2.7v) 105c 8 5c 25c -40c 0 5 10 15 20 25 3 0 3 5 40 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v re s et (v) i re s et (a) 105 c 8 5c 25c -40c 0 10 20 3 0 40 50 60 00. 3 0.6 0. 9 1.2 1.5 1. 8 2.1 2.4 2.7 v re s et (v) i re s et (a) 583 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-20.atmega168pa: reset pull-up resistor current vs. reset pin voltage (v cc = 5v) 34.7 pin driver strength figure 34-21.atmega168pa: i/o pin output voltage vs. sink current (v cc = 3v) 105c 8 5c 25c -40c 0 20 40 60 8 0 100 120 00.511.522.5 33 .5 4 4.5 5 v re s et (v) i re s et (a) 105c 8 5c 25c -40c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol (v) 584 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-22.atmega168pa: i/o pin output voltage vs. sink current (v cc = 5v) figure 34-23.atmega168pa: i/o pin ou tput voltage vs. source current (v cc = 3v) 105c 8 5c 25c -40c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol (v) 105c 8 5c 25c -40c 1.7 1. 9 2.1 2. 3 2.5 2.7 2. 9 3 .1 0 5 10 15 20 i oh (ma) v oh (v) 585 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-24.atmega168p a i/o pin output voltage vs. source current (v cc = 5v) 34.8 pin threshold and hysteresis figure 34-25.atmega168pa i/o pi n input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) 105c 8 5c 25c -40c 4. 3 4.4 4.5 4.6 4.7 4. 8 4. 9 5 0 5 10 15 20 i oh (ma) v oh (v) 105c 8 5c 25c -40c 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 2.6 2. 8 3 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 586 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-26.atmega168pa i/o pi n input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 34-27.atmega168pa i/ o pin input hysteresis vs. v cc 105c 8 5c 25c -40c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 105c 8 5c 25c -40c 0.25 0. 3 0. 3 5 0.4 0.45 0.5 0.55 0.6 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (v) 587 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-28.atmega168pa: reset input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 34-29.atmega168pa: reset input threshold voltage vs. v cc (v il , i/o pin read as ?0?) 105c 8 5c 25c -40c 0.6 0.7 0. 8 0. 9 1 1.1 1.2 1. 3 1.4 1.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 105c 8 5c 25c -40c 0.5 0.7 0. 9 1.1 1. 3 1.5 1.7 1. 9 2.1 2. 3 2.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 588 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-30.atmega168pa: r eset pin input hysteresis vs. v cc 34.9 bod threshold figure 34-31.atmeg a168pa: bod threshol ds vs. temperature (bodlevel is 1.8v) 105c 8 5c 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) inp u t hysteresis ( v ) ri s ing vcc f a lling vcc 1.76 1.77 1.7 8 1.7 9 1. 8 1. 8 1 1. 8 2 1. 83 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) thre s hold (v) 589 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-32.atmeg a168pa: bod threshol ds vs. temperature (bodlevel is 2.7v) figure 34-33.atmeg a168pa: bod threshol ds vs. temperature (bodlevel is 4.3v) f a lling vcc ri s ing vcc 2.62 2.64 2.66 2.6 8 2.7 2.72 2.74 2.76 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) thre s hold (v) ri s ing vcc f a lling vcc 4.2 4.22 4.24 4.26 4.2 8 4. 3 4. 3 2 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) thre s hold (v) 590 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-34.atmega168pa: cali brated bandgap voltage vs. vcc figure 34-35.atmega168pa: calibrat ed bandgap voltage vs. temperature 105c 8 5c 25c -40c 1.116 1.11 8 1.12 1.122 1.124 1.126 1.12 8 1.1 3 1.1 3 2 1.1 3 4 1.1 3 6 1.5 2 2.5 33 .5 4 4.5 5 5.5 vcc (v) b a ndg a p volt a ge (v) 5.5v 4.5v 4.0v 3 . 3 v 2.7v 1. 8 v 1.116 1.11 8 1.12 1.122 1.124 1.126 1.12 8 1.1 3 1.1 3 2 1.1 3 4 1.1 3 6 -50 - 3 0-10 10 3 05070 9 0110 temper a t u re (c) b a ndg a p volt a ge (v) 591 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 34.10 internal oscillator speed figure 34-36.atmega168pa: watchdog oscillator frequen cy vs. temperature figure 34-37.atmega168pa: watchd og oscillator frequency vs. v cc 5.5v 5.0v 4.5v 4.0v 3 . 3 v 2.7v 10 8 110 112 114 116 11 8 120 122 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0100 temper a t u re (c) f rc (khz) 105c 8 5c 25c -40c 10 8 110 112 114 116 11 8 120 122 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) f rc (khz) 592 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-38.atmega168pa: calibrated 8mhz rc oscillator frequency vs. v cc figure 34-39.atmega168pa: calibrated 8mhz rc oscillator frequency vs. temperature 105c 8 5c 25c -40c 7.5 7.6 7.7 7. 8 7. 9 8 8 .1 8 .2 8 . 3 8 .4 8 .5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) f rc (mhz) 5.5v 4.5v 4.0v 3 . 3 v 1. 8 v 7.5 7.6 7.7 7. 8 7. 9 8 8 .1 8 .2 8 . 3 8 .4 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) f rc (mhz) 593 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-40.atmega168pa: calibrated 8mhz rc oscillator frequency vs. osccal value 34.11 current consumpti on of peripheral units figure 34-41.atmega168pa: adc current vs. v cc (aref = av cc ) 105c 8 5c 25c -40c 2 4 6 8 10 12 14 016 3 24 8 64 8 0 9 611212 8 144 160 176 1 9 220 8 224 240 256 o s ccal (x1) f rc (mhz) 105c 8 5c 25c -40c 100 125 150 175 200 225 250 275 3 00 3 25 1.5 2 2.5 33 .544.555.5 v cc (v) i cc (a) 594 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-42.atmega168pa: anal og comparator current vs. v cc figure 34-43.atmega168pa: aref external reference current vs. v cc 105c 8 5c 25c -40c 3 0 40 50 60 70 8 0 9 0 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 40 60 8 0 100 120 140 160 1 8 0 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 595 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-44.atmega168pa: brow nout detector current vs. v cc figure 34-45.atmega168pa: programming current vs. v cc 105c 8 5c 25c -40c 14 16 1 8 20 22 24 26 2 8 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 1 2 3 4 5 6 7 8 9 1.5 2 2.5 33 .544.555.5 v cc (v) i cc (ma) 596 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 34.12 current consumption in reset and reset pulsewidth figure 34-46.atmega168pa: reset supply cu rrent vs. low frequency (0.1mhz - 1.0mhz) figure 34-47.atmega168pa: reset supply current vs. frequency (1mhz - 20mhz) 5.5v 4.5v 4.0v 3 . 3 v 2.7v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 5.5v 5.0v 4.5v 0 0. 3 0.6 0. 9 1.2 1.5 1. 8 2.1 2.4 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7v 3 .6v 4.0v 597 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 34-48.atmega168pa: mini mum reset pulse width vs. vcc 105c 8 5c 25c -40c 0 200 400 600 8 00 1000 1200 1400 1600 1 8 00 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) p u l s ewidth (n s ) 598 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 35. atmega328p typical characteristics ? (t a = -40c to 105c) the following charts show typical behavior. these figures are not tested during manufacturing. all current con- sumption measurements are performed with all i/o pins conf igured as inputs and with internal pull-ups enabled. a sine wave generator with rail-to-rail output is used as clock source. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors such as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient temperature. the dominating factors are operating voltage and frequency. the current drawn from capacitive loaded pins may be estimated (for one pin) as c l * v cc *f where c l = load capac- itance, v cc = operating voltage and f = average switching frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. the difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the di fferential current drawn by the watchdog timer. 35.1 atmega328p active supply current figure 35-1. atmega328p: active supply current vs. low frequency (0.1mhz - 1.0mhz) 5.5v 5.0v 4.5v 4.0v 3 .6v 2.7v 1. 8 v 0 0.2 0.4 0.6 0. 8 1 1.2 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 599 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-2. atmega328p: active supply current vs. frequency (1mhz - 20mhz) figure 35-3. atmega328p: active supply current vs. v cc (internal rc oscillator, 128khz) 5.5v 5.0v 4.5v 0 2 4 6 8 10 12 14 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7v 3 .6v 4.0v 105c 8 5c 25c -40c 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 600 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-4. atmega328p: active supply current vs. v cc (internal rc oscillator, 1mhz) figure 35-5. atmega328p: active supply current vs. v cc (internal rc oscillator, 8mhz) 105c 8 5c 25c -40c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 1 2 3 4 5 6 7 1.522.5 33 .544.555.5 v cc (v) i cc (ma) 601 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 35.2 idle supply current figure 35-6. atmega328p: idle supply current vs. low frequency (0.1mhz - 1.0mhz) figure 35-7. atmega328p: idle supply current vs. frequency (1mhz - 20mhz) 5.5v 5.0v 4.5v 4.0v 3 .6v 2.7v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0.1 8 0.2 0 0.2 0.4 0.6 0. 8 1 fre qu ency (mhz) i cc (ma) 5.5v 5.0v 4.5v 0 0.5 1 1.5 2 2.5 3 3 .5 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7v 3 .6v 4.0v 602 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-8. atmega328p: idle supply current vs. v cc (internal rc oscillator, 128khz) figure 35-9. atmega328p: idle supply current vs. v cc (internal rc oscillator, 1mhz) 105c 8 5c 25c -40c 0.005 0.01 0.015 0.02 0.025 0.0 3 0.0 3 5 0.04 0.045 0.05 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 0.1 0.15 0.2 0.25 0. 3 0. 3 5 0.4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 603 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-10.atmega328p idle supply curre nt vs. vcc (internal rc oscillator, 8mhz) 35.3 power-down supply current figure 35-11.atmega328p: powe r-down supply current vs. v cc (watchdog timer disabled) 105c 8 5c 25c -40c 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 105c 8 5c 25c -40c 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 604 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-12.atmega328p: power-down supply current vs. v cc (watchdog timer enabled) 35.4 power-save supply current figure 35-13.atmega328p: powe r-save supply current vs. v cc (watchdog timer disabled and 32khz crystal oscilla- tor running) 105c 8 5c 25c -40c 2 3 4 5 6 7 8 9 10 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 0 0.5 1 1.5 2 2.5 3 3 .5 4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 605 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 35.5 standby supply current figure 35-14.atmega328p: standby supply current vs. vcc (watchdog timer disabled) 35.6 pin pull-up figure 35-15.atmega328p: i/o pin pull-u p resistor current vs. input voltage (v cc = 1.8v) 6 mhz_xtal 6 mhz_res 4 mhz_xtal 4 mhz_res 2 mhz_xtal 2 mhz_res 1 mhz_res 0.02 0.03 0.04 0.05 0.06 0.07 0.0 8 0.09 0.1 0.11 0.12 0.13 0.14 0.15 2 2.5 3 3.5 4 4.5 5 5.5 v cc ( v ) i cc (ma) 105c 8 5c 25c -40c 0 5 10 15 20 25 30 35 40 45 50 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 v op ( v ) i op ( a) 606 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-16.atmega328p: i/o pin pull-u p resistor current vs. input voltage (v cc = 2.7v) figure 35-17.atmega328p: i/o pin pull-u p resistor current vs. input voltage (v cc = 5v) 105c 8 5c 25c -40c 0 10 20 3 0 40 50 60 70 8 0 0 0.5 1 1.5 2 2.5 3 v op (v) i op (a) 0 20 40 60 8 0 100 120 140 160 012 3 45 v op (v) i op (a) 105c 8 5c 25c -40c 607 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-18.atmega328p: reset pull-up re sistor current vs. reset pin voltage (v cc = 1.8v) figure 35-19.atmega328p: reset pull-up re sistor current vs. reset pin voltage (v cc = 2.7v) 105c 8 5c 25c -40c 0 5 10 15 20 25 3 0 3 5 40 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 v re s et (v) i re s et (a) 0 10 20 3 0 40 50 60 00. 3 0.6 0. 9 1.2 1.5 1. 8 2.1 2.4 2.7 v re s et (v) i re s et (a) 105c 8 5c 25c -40c 608 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-20.atmega328p: reset pull-up re sistor current vs. reset pin voltage (v cc = 5v) 35.7 pin driver strength figure 35-21.atmega328p: i/o pin ou tput voltage vs. sink current (v cc = 3v) 0 20 40 60 8 0 100 120 0 0.5 1 1.5 2 2.5 33 .5 4 4.5 5 v re s et (v) i re s et (a) 105c 8 5c 25c -40c 105c 8 5c 25c -40c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 0 5 10 15 20 i ol (ma) v ol (v) 609 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-22.atmega328p: i/o pin ou tput voltage vs. sink current (v cc = 5v) figure 35-23.atmega328p: i/o pin output voltage vs. source current (vcc = 3v) 105c 8 5c 25c -40c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0 5 10 15 20 i ol (ma) v ol (v) 105c 8 5c 25c -40c 1. 9 2.1 2. 3 2.5 2.7 2. 9 3 .1 0 5 10 15 20 i oh (ma) v oh (v) 610 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-24.atmega328p: i/o pin ou tput voltage vs. source current (v cc = 5v) 35.8 pin threshold and hysteresis figure 35-25.atmega328p: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) 105c 8 5c 25c -40c 4. 3 4.4 4.5 4.6 4.7 4. 8 4. 9 5 5.1 0 5 10 15 20 i oh (ma) v oh (v) 105c 8 5c 25c -40c 1 1. 3 1.6 1. 9 2.2 2.5 2. 8 3 .1 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 611 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-26.atmega328p: i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0? figure 35-27.atmega328p: i/o pin input hysteresis vs. v cc 105c 8 5c 25c -40c 0.2 0.5 0. 8 1.1 1.4 1.7 2 2. 3 2.6 1.5 2 2.5 33 .544.555.5 v cc (v) thre s hold (v) 105c 8 5c 25c -40c 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 1. 8 2. 3 2. 83 . 33 . 8 4. 3 4. 8 5. 3 v cc (v) inp u t hy s tere s i s (mv) 612 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-28.atmega328p: reset input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 35-29.atmega328p: reset input threshold voltage vs. v cc (v il , i/o pin read as ?0?) 105c 8 5c 25c -40c 0. 8 1 1.2 1.4 1.6 1. 8 2 2.2 2.4 2.6 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 105c 8 5c 25c -40c 0.5 0.7 0. 9 1.1 1. 3 1.5 1.7 1. 9 2.1 2. 3 2.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 613 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-30.atmega328p: reset pin input hysteresis vs. v cc 35.9 bod threshold figure 35-31.atmeg a328p: bod thresholds vs. temp erature (bodlevel is 1.8v) 105c 8 5c 25c -40c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (v) ri s ing vcc f a lling vcc 1.7 8 1.7 9 1. 8 1. 8 1 1. 8 2 1. 83 1. 8 4 -50 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) thre s hold (v) 614 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-32.atmeg a328p bod thresholds vs. temp erature (bodlevel is 2.7v) figure 35-33.atmeg a328p bod thresholds vs. temp erature (bodlevel is 4.3v) ri s ing vcc f a lling vcc 2.66 2.67 2.6 8 2.6 9 2.7 2.71 2.72 2.7 3 2.74 2.75 2.76 2.77 2.7 8 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) thre s hold (v) ri s ing vcc f a lling vcc 4.24 4.26 4.2 8 4. 3 4. 3 2 4. 3 4 4. 3 6 4. 38 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) thre s hold (v) 615 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-34.atmega328p: calibr ated bandgap voltage vs. vcc 35.10 internal oscillator speed figure 35-35.atmega328p: watchdog os cillator frequency vs. temperature 105c 8 5c 25c -40c 1.121 1.124 1.127 1.1 3 1.1 33 1.1 3 6 1.1 39 1.5 2 2.5 33 .5 4 4.5 5 5.5 vcc (v) b a ndg a p volt a ge (v) 5.5v 4.0v 3 .6v 2.7v 106 10 8 110 112 114 116 11 8 120 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) f rc (khz) 616 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-36.atmega328p ? c watchdog oscillator frequency vs. v cc figure 35-37.atmega328p: calibrated 8 mhz rc oscillator frequency vs. v cc 105c 8 5c 25c -40c 106 10 8 110 112 114 116 11 8 120 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) f rc (khz) 105c 8 5c 25c -40c 7.4 7.6 7. 8 8 8 .2 8 .4 8 .6 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) f rc (mhz) 617 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-38.atmega328p: calibrated 8mhz rc oscillator frequency vs. temperature figure 35-39.atmega328p cali brated 8mhz rc oscillator frequency vs. osccal value 5.5v 5.0v 4.5v 4.0v 3 .6v 2.7v 1. 8 v 7.5 7.6 7.7 7. 8 7. 9 8 8 .1 8 .2 8 . 3 8 .4 -40 - 3 0 -20 -10 0 10 20 3 040506070 8 0 9 0 100 110 temper a t u re (c) f rc (mhz) 105c 8 5c 25c -40c 4 5 6 7 8 9 10 11 12 1 3 14 016 3 24 8 64 8 0 9 6 112 12 8 144 160 176 1 9 220 8 224 240 o s ccal (x1) f rc (mhz) 618 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 35.11 current consumpti on of peripheral units figure 35-40.atmega328p: adc current vs. v cc (aref = av cc ) figure 35-41.atmega328p: anal og comparator current vs. v cc 105c 8 5c 25c -40c 40 60 8 0 100 120 140 160 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 3 0 40 50 60 70 8 0 9 0 100 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 619 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-42.atmega328p: aref ex ternal reference current vs. v cc figure 35-43.atmega328p: brownout detector current vs. v cc 105c 8 5c 25c -40c 40 60 8 0 100 120 140 160 1 8 0 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 105c 8 5c 25c -40c 10 15 20 25 3 0 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (a) 620 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-44.atmega328p: programming current vs. v cc 35.12 current consumption in reset and reset pulsewidth figure 35-45.atmega328p: reset supply current vs. low frequency (0.1mhz - 1.0mhz) 105c 8 5c 25c -40c 1 2 3 4 5 6 7 8 9 10 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 5.5v 5.0v 4.5v 4.0v 3 .6v 2.7v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.16 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0. 9 1 fre qu ency (mhz) i cc (ma) 621 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 figure 35-46.atmega328p reset supply current vs. frequency (1mhz - 20mhz) figure 35-47.atmega328p: mini mum reset pulse width vs. vcc 5.5v 5.0v 4.5v 0 0.5 1 1.5 2 2.5 3 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 4.0v 3 .6v 2.7v 1. 8 v 105c 8 5c 25c -40c 0 200 400 600 8 00 1000 1200 1400 1600 1 8 00 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) p u l s ewidth (n s ) 622 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 36. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved ? ? ? ? ? ? ? ? (0xfe) reserved ? ? ? ? ? ? ? ? (0xfd) reserved ? ? ? ? ? ? ? ? (0xfc) reserved ? ? ? ? ? ? ? ? (0xfb) reserved ? ? ? ? ? ? ? ? (0xfa) reserved ? ? ? ? ? ? ? ? (0xf9) reserved ? ? ? ? ? ? ? ? (0xf8) reserved ? ? ? ? ? ? ? ? (0xf7) reserved ? ? ? ? ? ? ? ? (0xf6) reserved ? ? ? ? ? ? ? ? (0xf5) reserved ? ? ? ? ? ? ? ? (0xf4) reserved ? ? ? ? ? ? ? ? (0xf3) reserved ? ? ? ? ? ? ? ? (0xf2) reserved ? ? ? ? ? ? ? ? (0xf1) reserved ? ? ? ? ? ? ? ? (0xf0) reserved ? ? ? ? ? ? ? ? (0xef) reserved ? ? ? ? ? ? ? ? (0xee) reserved ? ? ? ? ? ? ? ? (0xed) reserved ? ? ? ? ? ? ? ? (0xec) reserved ? ? ? ? ? ? ? ? (0xeb) reserved ? ? ? ? ? ? ? ? (0xea) reserved ? ? ? ? ? ? ? ? (0xe9) reserved ? ? ? ? ? ? ? ? (0xe8) reserved ? ? ? ? ? ? ? ? (0xe7) reserved ? ? ? ? ? ? ? ? (0xe6) reserved ? ? ? ? ? ? ? ? (0xe5) reserved ? ? ? ? ? ? ? ? (0xe4) reserved ? ? ? ? ? ? ? ? (0xe3) reserved ? ? ? ? ? ? ? ? (0xe2) reserved ? ? ? ? ? ? ? ? (0xe1) reserved ? ? ? ? ? ? ? ? (0xe0) reserved ? ? ? ? ? ? ? ? (0xdf) reserved ? ? ? ? ? ? ? ? (0xde) reserved ? ? ? ? ? ? ? ? (0xdd) reserved ? ? ? ? ? ? ? ? (0xdc) reserved ? ? ? ? ? ? ? ? (0xdb) reserved ? ? ? ? ? ? ? ? (0xda) reserved ? ? ? ? ? ? ? ? (0xd9) reserved ? ? ? ? ? ? ? ? (0xd8) reserved ? ? ? ? ? ? ? ? (0xd7) reserved ? ? ? ? ? ? ? ? (0xd6) reserved ? ? ? ? ? ? ? ? (0xd5) reserved ? ? ? ? ? ? ? ? (0xd4) reserved ? ? ? ? ? ? ? ? (0xd3) reserved ? ? ? ? ? ? ? ? (0xd2) reserved ? ? ? ? ? ? ? ? (0xd1) reserved ? ? ? ? ? ? ? ? (0xd0) reserved ? ? ? ? ? ? ? ? (0xcf) reserved ? ? ? ? ? ? ? ? (0xce) reserved ? ? ? ? ? ? ? ? (0xcd) reserved ? ? ? ? ? ? ? ? (0xcc) reserved ? ? ? ? ? ? ? ? (0xcb) reserved ? ? ? ? ? ? ? ? (0xca) reserved ? ? ? ? ? ? ? ? (0xc9) reserved ? ? ? ? ? ? ? ? (0xc8) reserved ? ? ? ? ? ? ? ? (0xc7) reserved ? ? ? ? ? ? ? ? (0xc6) udr0 usart i/o data register 194 (0xc5) ubrr0h usart baud rate register high 198 (0xc4) ubrr0l usart baud rate register low 198 (0xc3) reserved ? ? ? ? ? ? ? ? (0xc2) ucsr0c umsel01 umsel00 upm01 upm00 usbs0 ucsz01 /udord0 ucsz00 / ucpha0 ucpol0 196/207 (0xc1) ucsr0b rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 195 (0xc0) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 194 (0xbf) reserved ? ? ? ? ? ? ? ? (0xbe) reserved ? ? ? ? ? ? ? ? 623 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 (0xbd) twamr twam6 twam5 twam4 twam3 twam2 twam1 twam0 ?237 (0xbc) twcr twint twea twsta twsto twwc twen ?twie 235 (0xbb) twdr 2-wire serial interface data register 237 (0xba) twar twa6 twa5 twa4 tw a3 twa2 twa1 twa0 twgce 237 (0xb9) twsr tws7 tws6 tws5 tws4 tws3 ?twps1twps0 236 (0xb8) twbr 2-wire serial interface bit rate register 235 (0xb7) reserved ? ? ? ? ? ? ? (0xb6) assr ? exclk as2 tcn2ub ocr2aub ocr2bub tcr2aub tcr2bub 160 (0xb5) reserved ? ? ? ? ? ? ? ? (0xb4) ocr2b timer/counter2 output compare register b 159 (0xb3) ocr2a timer/counter2 output compare register a 159 (0xb2) tcnt2 timer/counter2 (8-bit) 159 (0xb1) tccr2b foc2a foc2b ? ? wgm22 cs22 cs21 cs20 158 (0xb0) tccr2a com2a1 com2a0 com2b1 com2b0 ? ?wgm21wgm20 155 (0xaf) reserved ? ? ? ? ? ? ? ? (0xae) reserved ? ? ? ? ? ? ? ? (0xad) reserved ? ? ? ? ? ? ? ? (0xac) reserved ? ? ? ? ? ? ? ? (0xab) reserved ? ? ? ? ? ? ? ? (0xaa) reserved ? ? ? ? ? ? ? ? (0xa9) reserved ? ? ? ? ? ? ? ? (0xa8) reserved ? ? ? ? ? ? ? ? (0xa7) reserved ? ? ? ? ? ? ? ? (0xa6) reserved ? ? ? ? ? ? ? ? (0xa5) reserved ? ? ? ? ? ? ? ? (0xa4) reserved ? ? ? ? ? ? ? ? (0xa3) reserved ? ? ? ? ? ? ? ? (0xa2) reserved ? ? ? ? ? ? ? ? (0xa1) reserved ? ? ? ? ? ? ? ? (0xa0) reserved ? ? ? ? ? ? ? ? (0x9f) reserved ? ? ? ? ? ? ? ? (0x9e) reserved ? ? ? ? ? ? ? ? (0x9d) reserved ? ? ? ? ? ? ? ? (0x9c) reserved ? ? ? ? ? ? ? ? (0x9b) reserved ? ? ? ? ? ? ? ? (0x9a) reserved ? ? ? ? ? ? ? ? (0x99) reserved ? ? ? ? ? ? ? ? (0x98) reserved ? ? ? ? ? ? ? ? (0x97) reserved ? ? ? ? ? ? ? ? (0x96) reserved ? ? ? ? ? ? ? ? (0x95) reserved ? ? ? ? ? ? ? ? (0x94) reserved ? ? ? ? ? ? ? ? (0x93) reserved ? ? ? ? ? ? ? ? (0x92) reserved ? ? ? ? ? ? ? ? (0x91) reserved ? ? ? ? ? ? ? ? (0x90) reserved ? ? ? ? ? ? ? ? (0x8f) reserved ? ? ? ? ? ? ? ? (0x8e) reserved ? ? ? ? ? ? ? ? (0x8d) reserved ? ? ? ? ? ? ? ? (0x8c) reserved ? ? ? ? ? ? ? ? (0x8b) ocr1bh timer/counter1 - output compare register b high byte 136 (0x8a) ocr1bl timer/counter1 - outp ut compare register b low byte 136 (0x89) ocr1ah timer/counter1 - output compare register a high byte 136 (0x88) ocr1al timer/counter1 - output compare register a low byte 136 (0x87) icr1h timer/counter1 - input capture register high byte 136 (0x86) icr1l timer/counter1 - input capture register low byte 136 (0x85) tcnt1h timer/counter1 - counter register high byte 135 (0x84) tcnt1l timer/counter1 - counter register low byte 135 (0x83) reserved ? ? ? ? ? ? ? ? (0x82) tccr1c foc1a foc1b ? ? ? ? ? ?135 (0x81) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 134 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 ? ?wgm11wgm10 132 (0x7f) didr1 ? ? ? ? ? ?ain1dain0d 241 (0x7e) didr0 ? ? adc5d adc4d adc3d adc2d adc1d adc0d 257 (0x7d) reserved ? ? ? ? ? ? ? ? (0x7c) admux refs1 refs0 adlar ? mux3 mux2 mux1 mux0 254 (0x7b) adcsrb ?acme ? ? ? adts2 adts1 adts0 257 (0x7a) adcsra aden adsc adate adif adie adps2 adps1 adps0 255 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 624 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 (0x79) adch adc data register high byte 256 (0x78) adcl adc data register low byte 256 (0x77) reserved ? ? ? ? ? ? ? ? (0x76) reserved ? ? ? ? ? ? ? ? (0x75) reserved ? ? ? ? ? ? ? ? (0x74) reserved ? ? ? ? ? ? ? ? (0x73) reserved ? ? ? ? ? ? ? ? (0x72) reserved ? ? ? ? ? ? ? ? (0x71) reserved ? ? ? ? ? ? ? ? (0x70) timsk2 ? ? ? ? ? ocie2b ocie2a toie2 159 (0x6f) timsk1 ? ?icie1 ? ? ocie1b ocie1a toie1 136 (0x6e) timsk0 ? ? ? ? ? ocie0b ocie0a toie0 110 (0x6d) pcmsk2 pcint23 pcint22 pcint21 pcint20 pcint19 pcint18 pcint17 pcint16 75 (0x6c) pcmsk1 ? pcint14 pcint13 pcint12 pcint11 pcint10 pcint9 pcint8 75 (0x6b) pcmsk0 pcint7 pcint6 pcint5 pc int4 pcint3 pcint2 pcint1 pcint0 75 (0x6a) reserved ? ? ? ? ? ? ? ? (0x69) eicra ? ? ? ?isc11isc10isc01isc00 72 (0x68) pcicr ? ? ? ? ? pcie2 pcie1 pcie0 (0x67) reserved ? ? ? ? ? ? ? ? (0x66) osccal oscillator calibration register 36 (0x65) reserved ? ? ? ? ? ? ? ? (0x64) prr prtwi prtim2 prtim0 ? prtim1 prspi prusart0 pradc 41 (0x63) reserved ? ? ? ? ? ? ? ? (0x62) reserved ? ? ? ? ? ? ? ? (0x61) clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 36 (0x60) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 54 0x3f (0x5f) sreg i t h s v n z c 9 0x3e (0x5e) sph ? ? ? ? ? (sp10) 5. sp9 sp8 12 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 12 0x3c (0x5c) reserved ? ? ? ? ? ? ? ? 0x3b (0x5b) reserved ? ? ? ? ? ? ? ? 0x3a (0x5a) reserved ? ? ? ? ? ? ? ? 0x39 (0x59) reserved ? ? ? ? ? ? ? ? 0x38 (0x58) reserved ? ? ? ? ? ? ? ? 0x37 (0x57) spmcsr spmie (rwwsb) 5. sigrd (rwwsre) 5. blbset pgwrt pgers spmen 283 0x36 (0x56) reserved ? ? ? ? ? ? ? ? 0x35 (0x55) mcucr ?bods (6) bodse (6) pud ? ? ivsel ivce 44/69/92 0x34 (0x54) mcusr ? ? ? ? wdrf borf extrf porf 54 0x33 (0x53) smcr ? ? ? ?sm2sm1sm0se 39 0x32 (0x52) reserved ? ? ? ? ? ? ? ? 0x31 (0x51) reserved ? ? ? ? ? ? ? ? 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 240 0x2f (0x4f) reserved ? ? ? ? ? ? ? ? 0x2e (0x4e) spdr spi data register 171 0x2d (0x4d) spsr spif wcol ? ? ? ? ? spi2x 170 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 169 0x2b (0x4b) gpior2 general purpose i/o register 2 25 0x2a (0x4a) gpior1 general purpose i/o register 1 25 0x29 (0x49) reserved ? ? ? ? ? ? ? ? 0x28 (0x48) ocr0b timer/counter0 output compare register b 0x27 (0x47) ocr0a timer/counter0 output compare register a 0x26 (0x46) tcnt0 timer/counter0 (8-bit) 0x25 (0x45) tccr0b foc0a foc0b ? ? wgm02 cs02 cs01 cs00 0x24 (0x44) tccr0a com0a1 com0a0 com0b1 com0b0 ? ?wgm01wgm00 0x23 (0x43) gtccr tsm ? ? ? ? ? psrasy psrsync 141/161 0x22 (0x42) eearh (eeprom address register high byte) 5. 21 0x21 (0x41) eearl eeprom address register low byte 21 0x20 (0x40) eedr eeprom data register 21 0x1f (0x3f) eecr ? ? eepm1 eepm0 eerie eempe eepe eere 21 0x1e (0x3e) gpior0 general purpose i/o register 0 25 0x1d (0x3d) eimsk ? ? ? ? ? ?int1int0 73 0x1c (0x3c) eifr ? ? ? ? ? ? intf1 intf0 73 0x1b (0x3b) pcifr ? ? ? ? ? pcif2 pcif1 pcif0 0x1a (0x3a) reserved ? ? ? ? ? ? ? ? 0x19 (0x39) reserved ? ? ? ? ? ? ? ? 0x18 (0x38) reserved ? ? ? ? ? ? ? ? 0x17 (0x37) tifr2 ? ? ? ? ? ocf2b ocf2a tov2 160 0x16 (0x36) tifr1 ? ?icf1 ? ? ocf1b ocf1a tov1 137 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 625 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specif ied bit, and can therefore be used on regi sters containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instruct ions, 0x20 must be added to these addresses. the atmega48a/pa/88a/pa/168a/pa/328/p is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and ou t instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 5. only valid for atmega88a/88pa/168a/168pa/328/328p. 6. bods and bodse only available for picopower devices atmega48pa/88pa/168pa/328p 0x15 (0x35) tifr0 ? ? ? ? ? ocf0b ocf0a tov0 0x14 (0x34) reserved ? ? ? ? ? ? ? ? 0x13 (0x33) reserved ? ? ? ? ? ? ? ? 0x12 (0x32) reserved ? ? ? ? ? ? ? ? 0x11 (0x31) reserved ? ? ? ? ? ? ? ? 0x10 (0x30) reserved ? ? ? ? ? ? ? ? 0x0f (0x2f) reserved ? ? ? ? ? ? ? ? 0x0e (0x2e) reserved ? ? ? ? ? ? ? ? 0x0d (0x2d) reserved ? ? ? ? ? ? ? ? 0x0c (0x2c) reserved ? ? ? ? ? ? ? ? 0x0b (0x2b) portd portd7 portd6 portd 5 portd4 portd3 portd2 portd1 portd0 93 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 93 0x09 (0x29) pind pind7 pind6 pi nd5 pind4 pind3 pind2 pind1 pind0 93 0x08 (0x28) portc ? portc6 portc5 portc4 portc3 portc2 portc1 portc0 92 0x07 (0x27) ddrc ? ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 92 0x06 (0x26) pinc ? pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 92 0x05 (0x25) portb portb7 portb6 portb 5 portb4 portb3 portb2 portb1 portb0 92 0x04 (0x24) ddrb ddb7 ddb6 ddb 5 ddb4 ddb3 ddb2 ddb1 ddb0 92 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 92 0x02 (0x22) reserved ? ? ? ? ? ? ? ? 0x01 (0x21) reserved ? ? ? ? ? ? ? ? 0x0 (0x20) reserved ? ? ? ? ? ? ? ? address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 626 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 37. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd ? rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd ? rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl ? rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd ? rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd ? rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd ? rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd ? rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl ? rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd ?? rd ? rr z,n,v 1 andi rd, k logical and register and constant rd ? rd ?? k z,n,v 1 or rd, rr logical or registers rd ? rd v rr z,n,v 1 ori rd, k logical or register and constant rd ?? rd v k z,n,v 1 eor rd, rr exclusive or registers rd ? rd ? rr z,n,v 1 com rd one?s complement rd ? 0xff ? rd z,c,n,v 1 neg rd two?s complement rd ? 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd ? rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd ? rd ? (0xff - k) z,n,v 1 inc rd increment rd ? rd + 1 z,n,v 1 dec rd decrement rd ? rd ? 1 z,n,v 1 tst rd test for zero or minus rd ? rd ? rd z,n,v 1 clr rd clear register rd ? rd ? rd z,n,v 1 ser rd set register rd ? 0xff none 1 mul rd, rr multiply unsigned r1:r0 ? rd x rr z,c 2 muls rd, rr multiply signed r1:r0 ? rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 ? rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 ? (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 ? (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 ? (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc ?? pc + k + 1 none 2 ijmp indirect jump to (z) pc ? z none 2 jmp (1) k direct jump pc ?? knone3 rcall k relative subroutine call pc ? pc + k + 1 none 3 icall indirect call to (z) pc ? znone3 call (1) k direct subroutine call pc ? knone4 ret subroutine return pc ? stack none 4 reti interrupt return pc ? stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc ?? pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc ? pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc ? pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc ? pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc ? pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc ? pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc ? pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc ? pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc ? pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc ? pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc ? pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc ? pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc ? pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc ? pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc ? pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n ? v= 0) then pc ? pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n ? v= 1) then pc ? pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc ? pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc ? pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc ? pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc ? pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc ? pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc ? pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc ? pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc ? pc + k + 1 none 1/2 627 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) ? 1none2 cbi p,b clear bit in i/o register i/o(p,b) ? 0none2 lsl rd logical shift left rd(n+1) ? rd(n), rd(0) ? 0 z,c,n,v 1 lsr rd logical shift right rd(n) ? rd(n+1), rd(7) ? 0 z,c,n,v 1 rol rd rotate left through carry rd(0) ? c,rd(n+1) ? rd(n),c ? rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) ? c,rd(n) ? rd(n+1),c ? rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) ? rd(n+1), n=0...6 z,c,n,v 1 swap rd swap nibbles rd(3...0) ? rd(7...4),rd(7...4) ? rd(3...0) none 1 bset s flag set sreg(s) ? 1 sreg(s) 1 bclr s flag clear sreg(s) ? 0 sreg(s) 1 bst rr, b bit store from register to t t ? rr(b) t 1 bld rd, b bit load from t to register rd(b) ? tnone1 sec set carry c ? 1c1 clc clear carry c ? 0 c 1 sen set negative flag n ? 1n1 cln clear negative flag n ? 0 n 1 sez set zero flag z ? 1z1 clz clear ze ro flag z ? 0 z 1 sei global interrupt enable i ? 1i1 cli global interrupt disable i ?? 0 i 1 ses set signed test flag s ? 1s1 cls clear signed test flag s ? 0 s 1 sev set twos complement overflow. v ? 1v1 clv clear twos complement overflow v ? 0 v 1 set set t in sreg t ? 1t1 clt clear t in sreg t ? 0 t 1 seh set half carry flag in sreg h ? 1h1 clh clear half carry flag in sreg h ? 0 h 1 data transfer instructions mov rd, rr move between registers rd ? rr none 1 movw rd, rr copy register word rd+1:rd ? rr+1:rr none 1 ldi rd, k load immediate rd ? knone1 ld rd, x load indirect rd ? (x) none 2 ld rd, x+ load indirect and post-inc. rd ? (x), x ? x + 1 none 2 ld rd, - x load indirect and pre-dec. x ? x - 1, rd ? (x) none 2 ld rd, y load indirect rd ? (y) none 2 ld rd, y+ load indirect and post-inc. rd ? (y), y ? y + 1 none 2 ld rd, - y load indirect and pre-dec. y ? y - 1, rd ? (y) none 2 ldd rd,y+q load indirect with displacement rd ? (y + q) none 2 ld rd, z load indirect rd ? (z) none 2 ld rd, z+ load indirect and post-inc. rd ? (z), z ? z+1 none 2 ld rd, -z load indirect and pre-dec. z ? z - 1, rd ? (z) none 2 ldd rd, z+q load indirect with displacement rd ? (z + q) none 2 lds rd, k load direct from sram rd ? (k) none 2 st x, rr store indirect (x) ?? rr none 2 st x+, rr store indirect and post-inc. (x) ?? rr, x ? x + 1 none 2 st - x, rr store indirect and pre-dec. x ? x - 1, (x) ? rr none 2 st y, rr store indirect (y) ? rr none 2 st y+, rr store indirect and post-inc. (y) ? rr, y ? y + 1 none 2 st - y, rr store indirect and pre-dec. y ? y - 1, (y) ? rr none 2 std y+q,rr store indirect with displacement (y + q) ? rr none 2 st z, rr store indirect (z) ? rr none 2 st z+, rr store indirect and post-inc. (z) ? rr, z ? z + 1 none 2 st -z, rr store indirect and pre-dec. z ? z - 1, (z) ? rr none 2 std z+q,rr store indirect with displacement (z + q) ? rr none 2 sts k, rr store direct to sram (k) ? rr none 2 lpm load program memory r0 ? (z) none 3 lpm rd, z load program memory rd ? (z) none 3 lpm rd, z+ load program memory and post-inc rd ? (z), z ? z+1 none 3 spm store program memory (z) ? r1:r0 none - in rd, p in port rd ? pnone1 out p, rr out port p ? rr none 1 push rr push register on stack stack ? rr none 2 pop rd pop register from stack rd ? stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 mnemonics operands description operation flags #clocks 628 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 note: 1. these instructions are only available in atmega168pa and atmega328p. wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks 629 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 38. ordering information 38.1 atmega48a note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substances (rohs directive). also halide free and fully green. 3. see ?speed grades? on page 310 . 4. nipdau lead finish. 5. tape & reel. 6. use ?atmega48pa? on page 630 , industrial (-40 ? c to 105 ? c) as the atmega48a (-40 ? c to 105 ? c) is not presently offered. speed (mhz) power supply (v) ordering code (2) package (1) operational range (6) 20 (3) 1.8 - 5.5 atmega48a-au atmega48a-aur (5) atmega48a-ccu atmega48a-ccur (5) atmega48a-mmh (4) atmega48a-mmhr (4)(5) atmega48a-mu atmega48a-mur (5) atmega48a-pu 32a 32a 32cc1 32cc1 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 ? c to 85 ? c) package type 32a 32-lead, thin (1.0 mm) plastic quad flat package (tqfp) 32cc1 32-ball, 4 x 4 x 0.6 mm package, ball pitch 0.5 mm , ultra thin, fine-pitch ball grill array (ufbga) 28m1 28-pad, 4 x 4 x 1.0 body, lead pitch 0.45 mm quad flat no-lead/micro lead frame package (qfn/mlf) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50 mm quad flat no-lead/micro lead frame package (qfn/mlf) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip) 630 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 38.2 atmega48pa note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substances (rohs directive). also halide free and fully green. 3. see ?speed grades? on page 310 . 4. nipdau lead finish. 5. tape & reel. speed (mhz) (3) power supply (v) ordering code (2) package (1) operational range 20 1.8 - 5.5 atmega48pa-au atmega48pa-aur (5) atmega48pa-ccu atmega48pa-ccur (5) atmega48pa-mmh (4) atmega48pa-mmhr (4)(5) atmega48pa-mu atmega48pa-mur (5) atmega48pa-pu 32a 32a 32cc1 32cc1 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 ? c to 85 ? c) atmega48pa-an atmega48pa-anr (5) atmega48pa-mmn (4) atmega48pa-mmnr (4)(5) atmega48pa-mn atmega48pa-mnr (5) atmega48pa-pn 32a 32a 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 ? c to 105 ? c) package type 32a 32-lead, thin (1.0mm) plastic quad flat package (tqfp) 32cc1 32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, ultra thin, fine-pitch ball grill array (ufbga) 28m1 28-pad, 4 x 4 x 1.0 body, lead pitch 0.45mm quad flat no-lead/micro lead frame package (qfn/mlf) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50mm quad flat no-lead/micro lead frame package (qfn/mlf) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip) 631 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 38.3 atmega88a note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substa nces (rohs directive).also halide free and fully green. 3. see ?speed grades? on page 310 . 4. nipdau lead finish. 5. tape & reel. 6. use ?atmega88pa? on page 632 , industrial (-40 ? c to 105 ? c) as the atmega48a (-40 ? c to 105 ? c) is not presently offered. speed (mhz) power supply (v) ordering code (2) package (1) operational range (6) 20 (3) 1.8 - 5.5 atmega88a-au atmega88a-aur (5) atmega88a-ccu atmega88a-ccur (5) atmega88a-mmh (4) atmega88a-mmhr (4)(5) atmega88a-mu atmega88a-mur (5) atmega88a-pu 32a 32a 32cc1 32cc1 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 ? c to 85 ? c) package type 32a 32-lead, thin (1.0mm) plastic quad flat package (tqfp) 32cc1 32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, ultra thin, fine-pitch ball grill array (ufbga) 28m1 28-pad, 4 x 4 x 1.0 body, lead pitch 0.45mm quad flat no-lead/micro lead frame package (qfn/mlf) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50mm quad flat no-lead/micro lead frame package (qfn/mlf) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip) 632 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 38.4 atmega88pa note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substa nces (rohs directive).also halide free and fully green. 3. see ?speed grades? on page 310 . 4. nipdau lead finish. 5. tape & reel. speed (mhz) (3) power supply (v) ordering code (2) package (1) operational range 20 1.8 - 5.5 atmega88pa-au atmega88pa-aur (5) atmega88pa-ccu atmega88pa-ccur (5) atmega88pa-mmh (4) atmega88pa-mmhr (4)(5) atmega88pa-mu atmega88pa-mur (5) atmega88pa-pu 32a 32a 32cc1 32cc1 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 ? c to 85 ? c) atmega88pa-an atmega88pa-anr (5) atmega88pa-mmn (4) atmega88pa-mmnr (4)(5) atmega88pa-mn atmega88pa-mnr (5) atmega88pa-pn 32a 32a 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 ? c to 105 ? c) package type 32a 32-lead, thin (1.0mm) plastic quad flat package (tqfp) 32cc1 32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5 mm, ultra thin, fine-pitch ball grill array (ufbga) 28m1 28-pad, 4 x 4 x 1.0 body, lead pitch 0.45 mm quad flat no-lead/micro lead frame package (qfn/mlf) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50 mm quad flat no-lead/micro lead frame package (qfn/mlf) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip) 633 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 38.5 atmega168a note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substa nces (rohs directive).also halide free and fully green. 3. see ?speed grades? on page 310 4. nipdau lead finish. 5. tape & reel. 6. use ?atmega168pa? on page 634 , industrial (-40 ? c to 105 ? c) as the atmega48a (-40 ? c to 105 ? c) is not presently offered. speed (mhz) (3) power supply (v) ordering code (2) package (1) operational range (6) 20 1.8 - 5.5 atmega168a-au atmega168a-aur (5) atmega168a-ccu atmega168a-ccur (5) atmega168a-mmh (4) atmega168a-mmhr (4)(5) atmega168a-mu atmega168a-mur (5) atmega168a-pu 32a 32a 32cc1 32cc1 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 ? c to 85 ? c) package type 32a 32-lead, thin (1.0mm) plastic quad flat package (tqfp) 32cc1 32-ball, 4 x 4 x 0.6 mm package, ball pitch 0.5mm, ultra thin, fine-pitch ball grill array (ufbga) 28m1 28-pad, 4 x 4 x 1.0 body, lead pitch 0.45mm quad flat no-lead/micro lead frame package (qfn/mlf) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50mm quad flat no-lead/micro lead frame package (qfn/mlf) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip) 634 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 38.6 atmega168pa note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substa nces (rohs directive).also halide free and fully green. 3. see ?speed grades? on page 310 . 4. nipdau lead finish. 5. tape & reel. speed (mhz) (3) power supply (v) ordering code (2) package (1) operational range 20 1.8 - 5.5 atmega168pa-au atmega168pa-aur (5) atmega168pa-ccu atmega168pa-ccur (5) atmega168pa-mmh (4) atmega168pa-mmhr (4)(5) atmega168pa-mu atmega168pa-mur (5) atmega168pa-pu 32a 32a 32cc1 32cc1 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 ? c to 85 ? c) 20 1.8 - 5.5 atmega168pa-an atmega168pa-anr (5) atmega168pa-mn atmega168pa-mnr (5) atmega168pa-pn 32a 32a 32m1-a 32m1-a 28p3 industrial (-40 ? c to 105 ? c) package type 32a 32-lead, thin (1.0mm) plastic quad flat package (tqfp) 32cc1 32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, ultra thin, fine-pitch ball grill array (ufbga) 28m1 28-pad, 4 x 4 x 1.0 body, lead pitch 0.45mm quad flat no-lead/micro lead frame package (qfn/mlf) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50mm quad flat no-lead/micro lead frame package (qfn/mlf) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip) 635 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 38.7 atmega328 note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substa nces (rohs directive).also halide free and fully green. 3. see figure 29-1 on page 310 . 4. nipdau lead finish. 5. tape & reel 6. use ?atmega328p? on page 636 , industrial (-40 ? c to 105 ? c) as the atmega48a (-40 ? c to 105 ? c) is not presently offered. speed (mhz) power supply (v) ordering code (2) package (1) operational range (6) 20 (3) 1.8 - 5.5 atmega328-au atmega328-aur (5) atmega328-mmh (4) atmega328-mmhr (4)(5) atmega328-mu atmega328-mur (5) atmega328-pu 32a 32a 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 ? c to 85 ? c) package type 32a 32-lead, thin (1.0mm) plastic quad flat package (tqfp) 28m1 28-pad, 4 x 4 x 1.0 body, lead pitch 0.45mm quad flat no-lead/micro lead frame package (qfn/mlf) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50mm quad flat no-lead/micro lead frame package (qfn/mlf) 636 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 38.8 atmega328p note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substa nces (rohs directive).also halide free and fully green. 3. see figure 29-1 on page 310 . 4. nipdau lead finish. 5. tape & reel. speed (mhz) (3) power supply (v) ordering code (2) package (1) operational range 20 1.8 - 5.5 atmega328p-au atmega328p-aur (5) atmega328p-mmh (4) atmega328p-mmhr (4)(5) atmega328p-mu atmega328p-mur (5) atmega328p-pu 32a 32a 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 ? c to 85 ? c) atmega328p-an atmega328p-anr (5) atmega328p-mn atmega328p-mnr (5) atmega328p-pn 32a 32a 32m1-a 32m1-a 28p3 industrial (-40 ? c to 105 ? c) package type 32a 32-lead, thin (1.0mm) plastic quad flat package (tqfp) 28m1 28-pad, 4 x 4 x 1.0 body, lead pitch 0.45mm quad flat no-lead/micro lead frame package (qfn/mlf) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50mm quad flat no-lead/micro lead frame package (qfn/mlf) 637 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 39. packaging information 39.1 32a title drawing no. rev. 32a, 32-lead, 7 x 7mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (tqfp) c 32a 2010-10-20 pin 1 identifier 0~7 pin 1 l c a1 a2 a d1 d e e1 e b notes: 1. this package conforms to jedec reference ms-026, variation aba. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10mm maximum. a C C 1.20 a1 0.05 C 0.15 a2 0.95 1.00 1.05 d 8.75 9.00 9.25 d1 6.90 7.00 7.10 note 2 e 8.75 9.00 9.25 e1 6.90 7.00 7.10 note 2 b 0.30 C 0.45 c 0.09 C 0.20 l 0.45 C 0.75 e 0.80 typ common dimensions (unit of measure = mm) symbol min nom max note 638 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 39.2 32cc1 title drawing no. gpc rev. packa g e drawin g contact: packagedra w ings@atmel.com b cag 3 2cc1 , 32- b all (6 x 6 array), 4 x 4 x 0.6 mm package, b all pitch 0.50 mm, ultra thin, fine-pitch ball grid array (ufbga) 32cc1 a ? ? 0.60 a1 0.12 ? ? a2 0.3 8 ref b 0.25 0.30 0.35 1 b 1 0.25 ? ? 2 d 3.90 4.00 4.10 d1 2.50 bsc e 3.90 4.00 4.10 e1 2.50 bsc e 0.50 bsc 07/06/10 b 1 common dimen s ion s (unit of meas u re = mm) 123456 b a c d e f e d e 32-? b e d b a pin#1 id 0.0 8 a1 a d1 e1 a2 a1 ball cor n er 123456 f c s ide view bottom view top view s ymbol min nom max note n ote1: dimension ?b? is measured at the maximum ball dia. in a plane parallel to the seating plane. n ote2: dimension ? b 1? is the soldera b le s u rface defined b y the opening of the solder resist layer. e 639 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 39.3 28m1 title drawing no. gpc rev. packa g e drawin g contact: p a ck a gedr a wing s @ a tmel.com 2 8 m1 zbv b 2 8 m1, 28-pad, 4 x 4 x 1.0mm body, lead pitch 0.45mm, 2.4 x 2.4mm exposed pad, thermally enhanced plastic very thin quad flat no lead package (vqfn) 10/24/0 8 s ide view pin 1 id bottom view top view note: the termin a l #1 id i s a l as er-m a rked fe a t u re . d e e k a1 c a d2 e2 y l 1 2 3 b 1 2 3 0.45 common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a 0. 8 0 0. 9 0 1.00 a1 0.00 0.02 0.05 b 0.17 0.22 0.27 c 0.20 ref d 3 . 9 5 4.00 4.05 d2 2. 3 5 2.40 2.45 e 3 . 9 5 4.00 4.05 e2 2. 3 5 2.40 2.45 e 0.45 l 0. 3 5 0.40 0.45 y 0.00 ? 0.0 8 k 0.20 ? ? r 0.20 0.4 ref (4x) 640 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 39.4 32m1-a 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 9 51 3 1 title drawing no. r rev. 3 2m1-a , 3 2-p a d, 5 x 5 x 1.0mm body, le a d pitch 0.50mm, e 3 2m1-a 5/25/06 3 .10mm expo s ed p a d, micro le a d fr a me p a ck a ge (mlf) common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note d1 d e1 e e b a 3 a2 a1 a d2 e2 0.0 8 c l 1 2 3 p p 0 1 2 3 a 0. 8 0 0. 9 0 1.00 a1 ? 0.02 0.05 a2 ? 0.65 1.00 a 3 0.20 ref b 0.1 8 0.2 3 0. 3 0 d d1 d2 2. 9 5 3 .10 3 .25 4. 9 0 5.00 5.10 4.70 4.75 4. 8 0 4.70 4.75 4. 8 0 4. 9 0 5.00 5.10 e e1 e2 2. 9 5 3 .10 3 .25 e 0.50 b s c l 0. 3 0 0.40 0.50 p ? ? 0.60 ? ? 12 o note: jedec s t a nd a rd mo-220, fig. 2 (anvil s ing u l a tion), vhhd-2. top view s ide view bottom view 0 pin 1 id pin #1 notch (0.20 r) k 0.20 ? ? k k 641 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 39.5 28p3 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 9 51 3 1 title drawing no. r rev. 2 8 p 3 , 2 8 -le a d (0. 3 00"/7.62mm wide) pl as tic d ua l inline p a ck a ge (pdip) b 2 8 p 3 0 9 /2 8 /01 pin 1 e1 a1 b ref e b1 c l s eating plane a 0o ~ 15o d e eb b2 (4 place s ) common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a ? ? 4.5724 a1 0.50 8 ? ? d 3 4.544 ? 3 4.7 98 note 1 e 7.620 ? 8 .255 e1 7.112 ? 7.4 93 note 1 b 0. 38 1 ? 0.5 33 b1 1.14 3 ? 1. 39 7 b2 0.762 ? 1.14 3 l 3 .175 ? 3 .42 9 c 0.20 3 ? 0. 3 56 eb ? ? 10.160 e 2.540 typ note: 1. dimen s ion s d a nd e1 do not incl u de mold fl as h or protr us ion. mold fl as h or protr us ion s h a ll not exceed 0.25mm (0.010"). 642 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 40. errata 40.1 errata atmega48a the revision letter in this section refers to the revision of the atmega48a device. 40.1.1 rev. d ? analog mux can be turned off when setting acme bit ? twi data setup time can be too short 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer enabled) bi t in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 2. twi data setup time can be too short when running the device as a twi slave with a system clock above 2mhz, the data se tup time for the first bit after ack may in some cases be too short. this may cause a false start or stop condition on the twi line. problem fix/workaround insert a delay between setting twdr and twcr. 40.2 errata atmega48pa the revision letter in this section refers to the revision of the atmega48pa device. 40.2.1 rev. d ? analog mux can be turned off when setting acme bit ? twi data setup time can be too short 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer enabled) bi t in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 2. twi data setup time can be too short when running the device as a twi slave with a system clock above 2mhz, the data se tup time for the first bit after ack may in some cases be too short. this may cause a false start or stop condition on the twi line. problem fix/workaround insert a delay between setting twdr and twcr. 643 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 40.3 errata atmega88a the revision letter in this section refers to the revision of the atmega88a device. 40.3.1 rev. f ? analog mux can be turned off when setting acme bit ? twi data setup time can be too short 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer enabled) bi t in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 2. twi data setup time can be too short when running the device as a twi slave with a system clock above 2mhz, the data se tup time for the first bit after ack may in some cases be too short. this may cause a false start or stop condition on the twi line. problem fix/workaround insert a delay between setting twdr and twcr. 40.4 errata atmega88pa the revision letter in this section refers to the revision of the atmega88pa device. 40.4.1 rev. f ? analog mux can be turned off when setting acme bit ? twi data setup time can be too short 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer enabled) bi t in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 2. twi data setup time can be too short when running the device as a twi slave with a system clock above 2mhz, the data se tup time for the first bit after ack may in some cases be too short. this may cause a false start or stop condition on the twi line. problem fix/workaround insert a delay between setting twdr and twcr. 644 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 40.5 errata atmega168a the revision letter in this section refers to the revision of the atmega168a device. 40.5.1 rev. e ? analog mux can be turned off when setting acme bit ? twi data setup time can be too short 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer enabled) bi t in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 2. twi data setup time can be too short when running the device as a twi slave with a system clock above 2mhz, the data se tup time for the first bit after ack may in some cases be too short. this may cause a false start or stop condition on the twi line. problem fix/workaround insert a delay between setting twdr and twcr. 40.6 errata atmega168pa the revision letter in this section refers to the revision of the atmega168pa device. 40.6.1 rev e ? analog mux can be turned off when setting acme bit ? twi data setup time can be too short 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer enabled) bi t in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 2. twi data setup time can be too short when running the device as a twi slave with a system clock above 2mhz, the data se tup time for the first bit after ack may in some cases be too short. this may cause a false start or stop condition on the twi line. problem fix/workaround insert a delay between setting twdr and twcr. 645 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 40.7 errata atmega328 the revision letter in this section refers to the revision of the atmega328 device. 40.7.1 rev d ? analog mux can be turned off when setting acme bit ? twi data setup time can be too short 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer enabled) bi t in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 2. twi data setup time can be too short when running the device as a twi slave with a system clock above 2mhz, the data se tup time for the first bit after ack may in some cases be too short. this may cause a false start or stop condition on the twi line. problem fix/workaround insert a delay between setting twdr and twcr. 40.7.2 rev c not sampled. 40.7.3 rev b ? analog mux can be turned off when setting acme bit ? unstable 32khz oscillator 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer enabled) bi t in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 2. unstable 32khz oscillator the 32khz oscillator does not work as system clock. the 32khz oscilla tor used as asynchronous timer is inaccurate. problem fix/ workaround none. 40.7.4 rev a ? analog mux can be turned off when setting acme bit ? unstable 32khz oscillator 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer enabled) bi t in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 646 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 2. unstable 32khz oscillator the 32khz oscillator does not work as system clock. the 32khz oscilla tor used as asynchronous timer is inaccurate. problem fix/ workaround none. 40.8 errata atmega328p the revision letter in this section refers to the revision of the atmega328p device. 40.8.1 rev d ? analog mux can be turned off when setting acme bit ? twi data setup time can be too short 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer enabled) bi t in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 2. twi data setup time can be too short when running the device as a twi slave with a system clock above 2mhz, the data se tup time for the first bit after ack may in some cases be too short. this may cause a false start or stop condition on the twi line. problem fix/workaround insert a delay between setting twdr and twcr. 40.8.2 rev c not sampled. 40.8.3 rev b ? analog mux can be turned off when setting acme bit ? unstable 32khz oscillator 1. analog mux can be turned off when setting acme bit if the acme (analog comparator multiplexer enabled) bi t in adcsrb is set while mux3 in admux is '1' (admux[3:0]=1xxx), all mux'es are turned off until the acme bit is cleared. problem fix/workaround clear the mux3 bit before setting the acme bit. 2. unstable 32khz oscillator the 32khz oscillator does not work as system clock. the 32khz oscilla tor used as asynchronous timer is inaccurate. problem fix/ workaround none. 647 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 40.8.4 rev a ? unstable 32khz oscillator 1. unstable 32khz oscillator the 32khz oscillator does not work as system clock. the 32khz oscilla tor used as asynchronous timer is inaccurate. problem fix/ workaround none. 648 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 41. datasheet revision history please note that the referring page numbers in this section are referred to this document. the referring revision in this section are referring to the document revision. 41.1 rev. 8271g ? 02/2013 41.2 rev. 8271f ? 08/2012 41.3 rev. 8271e ? 07/2012 1. added ?electrical characteristics (ta = -40c to 105c)? on page 320 . 2. added ?atmega48pa typical characteristics ? (ta = -40c to 105c)? on page 525 . 3. added ?atmega88pa typical characteristics ? (ta = -40c to 105c)? on page 549 . 4. added ?atmega168pa typical characteristics ? (ta = -40c to 105c)? on page 573 . 5. added ?atmega328p typical characteristics ? (ta = -40c to 105c)? on page 598 . 1. added ?dc characteristics? on page 303 . the following tables for dc characteristics - t a = -40 ? c to 105 ? c added: table 29-4 on page 305 table 29-7 on page 307 table 29-10 on page 308 table 29-13 on page 310 2. replaced the following typical characteristics by the plots that include les characteristics at ?t a =-40 ? c to 105 ? c?: ?atmega48pa typical characteristics? on page 350 ?atmega88pa typical characteristics? on page 399 ?atmega168pa typical characteristics? on page 450 ?atmega328p typical characteristics? on page 500 3. removed the power save (psave) maximum numbers for all devices throughout ?electrical characteristics ? (ta = -40c to 85c)? on page 303 . 4. changed the powerdown maximum numbers from 8.5 and 3a to 10 and 5 a (atmega48pa, atmega88pa, atmega168pa and atmega328p). 5. changed the table note ?maximum values are characteriz ed values and not test limits in production? to ?max values are test limits in production throughout ?electrical characteristics ? (ta = -40c to 85c)? on page 303 . 1. updated figure 1-1 on page 2 . overlined ?reset? in 28 mlf to p view and in 32 mlf top view. 2. added eear9 bit to the ?eearh and eearl ? the eeprom address register? on page 21 and updated the all bit descriptions accordingly. 3. added a footnote ?eear9 and eear8 ar e unused bits in atmega48a/48pa and must always be written to zero? to ?eearh and eearl ? the eeprom address register? on page 21 . 4. updated table 18-8 on page 157 , ?waveform generation mode bit description? . wgm2, wgm1 and wgm0 changed to wgm22, wgm21 and wgm20 respectively. 5. updated ?tccr2b ? timer/counter control register b? on page 158 . bit 2 (cs22) and bit 3 (wgm22) changed from r (read only) to r/w (read/write). 6. updated the definition of fosc on page 174 . fosc is the system clock frequen cy (not xtal pin frequency) 7. updated ?spmcsr ? store program memory control and status register? on page 267 . bit 0 renamed spmen and added bit 5 ?sigrd?. 8. replaced ?selfprgen? by ?spmen? throughout the whole datasheet including in the ?c ode examples?, except in ?program and data memory lock bits? on page 285 and in ?fuse bits? on page 286 . 9. updated ?register summary? on page 622 to include the bits: sigrd and spmen in the smpcsr register. 649 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 41.4 rev. 8271d ? 05/11 41.5 rev. 8271c ? 08/10 41.6 rev. 8271b ? 04/10 10. updated the table 29-1 on page 303 . removed the footnote. 11. updated the fo otnote of the table 29-18 on page 313 . removed the footnote ?note 2?. 12. updated ?errata? on page 642 . added ?errata? twi data setup time can be too short. 1. added atmel qtouch sensing capability feature 2. updated ?register description? on page 92 with pinxn as r/w. 3. added a footnote to the pinxn, page 92 . 4. updated ?ordering information? , ?atmega328? on page 635 . added ?atmega328-mmh? and ?atmega328-mmhr?. 5. updated ?ordering information? , ?atmega328p? on page 636 . added ?atmega328p-mmh? and ?atmega328p- mmhr?. 6. added ?ordering information? for atmega48pa/88pa/168pa/328p @ 105 ? c 7. updated ?errata atmega328? on page 645 and ?errata atmega328p? on page 646 8. updated the datasheet according to the atmel new brand style guide. 1. added 32ufbga pinout, table 1-1 on page 2 . 2. updated the ?sram data memory? , figure 8-3 on page 18 . 3. updated ?ordering information? on page 629 with ccu and ccur code related to ?32cc1? package drawing. 4. ?32cc1? package drawing added ?packaging information? on page 637 . 1. updated table 9-8 with correct value for time r oscillator at xtal2/tos2 2. corrected use of sbis instructions in assembly code examples. 3. corrected bod and bodse bits to r/w in section 10.11.2 on page 44 , section 12.5 on page 69 and section 14.4 on page 92 4. figures for bandgap characterization added, figure 31-34 on page 342 , figure 31-81 on page 367 , figure 31-128 on page 392 , figure 31-176 on page 418 , figure 31-223 on page 442 , figure 31-271 on page 468 , figure 31-318 on page 492 and figure 31-365 on page 517 . 5. updated ?packaging information? on page 637 by replacing 28m1 with a correct corresponding package. 650 atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 41.7 rev. 8271a ? 12/09 1. new datasheet 8271 with merged information for atmega48pa, atmega88pa, atmega168pa and atmega48a, atmega88a andatmega168a. also included information on atmega328 and atmega328p 2 changes done: ? new devices added: atmega48a/atmega88a/atmega168a and atmega328 ? updated feature description ? updated table 2-1 on page 6 ? added note for bod disable on page 39 . ? added note on bod and bodse in ?mcucr ? mcu control register? on page 92 and ?register description? on page 283 ? added limitation informatin for the application ?boot loader support ? read-while-write self- programming? on page 269 ? added limitiation information for ?program and data memory lock bits? on page 285 ? added specified dc characteristics ? added typical characteristics ? removed exception information in ?address match unit? on page 216 . i atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 table of contents features ................. ................ .............. .............. .............. .............. ............ 1 1 pin configurations ... ................. ................ ................ ................. .............. 2 1.1pin descriptions .........................................................................................................3 2 overview ................. .............. .............. .............. .............. .............. ............ 5 2.1block diagram ...........................................................................................................5 2.2comparison between processors .............................................................................6 3 resources ................. ................. ................ ................ ................. .............. 7 4 data retention ................. ................. ................ .............. .............. ............ 7 5 about code examples .. ................ ................. ................ .............. ............ 7 6 capacitive touch sensing ........ ................ ................ ................. .............. 7 7 avr cpu core ................. ................. ................ .............. .............. ............ 8 7.1overview ................................................................................................................... .8 7.2alu ? arithmetic logic unit .......................................................................................9 7.3status register ..........................................................................................................9 7.4general purpose register file ................................................................................10 7.5stack pointer ...........................................................................................................12 7.6instruction execution timing ...................................................................................13 7.7reset and interrupt handling ...................................................................................13 8 avr memories ........ ................ ................. ................ ................. .............. 16 8.1overview ..................................................................................................................1 6 8.2in-system reprogrammable flash program memory .............................................16 8.3sram data memory ................................................................................................18 8.4eeprom data memory ...... ................ ................ ................. ............ ............. ..........19 8.5i/o memory ..............................................................................................................20 8.6register description ................................................................................................21 9 system clock and clock opti ons ................. .............. .............. ............ 26 9.1clock systems and their distribution .......................................................................26 9.2clock sources .........................................................................................................27 9.3low power crystal oscillato r ...................................................................................28 9.4full swing crystal oscillator ....................................................................................29 9.5low frequency crystal osc illator ............................................................................31 9.6calibrated internal rc oscillator ............ .................................................................32 ii atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 9.7128khz internal oscillator .......................................................................................33 9.8external clock .........................................................................................................33 9.9clock output buffer .................................................................................................34 9.10timer/counter oscillator ........................................................................................34 9.11system clock prescaler ........................................................................................34 9.12register description ..............................................................................................36 10 power management and sleep m odes ............. .............. ............ .......... 38 10.1sleep modes ..........................................................................................................38 10.2bod disable (1) .......................................................................................................39 10.3idle mode ...............................................................................................................39 10.4adc noise reduction mode ..................................................................................39 10.5power-down mode .................................................................................................39 10.6power-save mode ..................................................................................................40 10.7standby mode .......................................................................................................40 10.8extended standby mode .......................................................................................41 10.9power reduction register .....................................................................................41 10.10minimizing power consumption ..........................................................................41 10.11register description ............................................................................................43 11 system control and reset .... ............. .............. .............. .............. .......... 46 11.1resetting the avr .................................................................................................46 11.2reset sources .......................................................................................................46 11.3power-on reset .....................................................................................................47 11.4external reset .......................................................................................................48 11.5brown-out detection ..............................................................................................48 11.6watchdog system reset .......................................................................................49 11.7internal voltage reference ....................................................................................49 11.8watchdog timer ....................................................................................................50 11.9register description ..............................................................................................54 12 interrupts ............... .............. .............. .............. .............. .............. ............ 57 12.1interrupt vectors in atmega48a and atmega48pa .............................................57 12.2interrupt vectors in atmega88a and atmega88pa .............................................59 12.3interrupt vectors in atmega168a and atmega168pa .........................................62 12.4interrupt vectors in atmega328 and atmega328p ..............................................65 12.5register description ..............................................................................................69 13 external interrupts ........ ................ ................. .............. .............. ............ 71 iii atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 13.1pin change interrupt timing ..................................................................................71 13.2register description ..............................................................................................72 14 i/o-ports ......... ................ ................ ................. .............. .............. ............ 76 14.1overview ................................................................................................................76 14.2ports as general digital i/o ...................................................................................77 14.3alternate port functions ........................................................................................81 14.4register description ..............................................................................................92 15 8-bit timer/counter0 with pw m .................... .............. .............. ............ 94 15.1features ................................................................................................................94 15.2overview ................................................................................................................94 15.3timer/counter clock sources ...............................................................................95 15.4counter unit ..........................................................................................................95 15.5output compare unit .............................................................................................96 15.6compare match output unit ..................................................................................98 15.7modes of operation ...............................................................................................99 15.8timer/counter timing diagrams .........................................................................103 15.9register description ............................................................................................105 16 16-bit timer/counter1 with pw m .................. .............. .............. .......... 112 16.1features ..............................................................................................................112 16.2overview ..............................................................................................................112 16.3accessing 16-bit registers ..................................................................................114 16.4timer/counter clock sources .............................................................................117 16.5counter unit ........................................................................................................118 16.6input capture unit ...............................................................................................118 16.7output compare units .........................................................................................120 16.8compare match output unit ................................................................................122 16.9modes of operation .............................................................................................123 16.10timer/counter timing diagrams .......................................................................130 16.11register description ..........................................................................................132 17 timer/counter0 and time r/counter1 prescalers ....... .............. .......... 139 17.1internal clock source ..........................................................................................139 17.2prescaler reset ...................................................................................................139 17.3external clock source .........................................................................................139 17.4register description ............................................................................................141 18 8-bit timer/counter2 with pwm and asynchronous operation ....... 142 iv atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 18.1features ..............................................................................................................142 18.2overview ..............................................................................................................142 18.3timer/counter clock sources .............................................................................143 18.4counter unit ........................................................................................................143 18.5output compare unit ...........................................................................................144 18.6compare match output unit ................................................................................146 18.7modes of operation .............................................................................................147 18.8timer/counter timing diagrams .........................................................................151 18.9asynchronous operation of timer/counter2 .......................................................153 18.10timer/counter prescaler ...................................................................................154 18.11register description ..........................................................................................155 19 spi ? serial peripheral in terface ................ ................. .............. .......... 162 19.1features ..............................................................................................................162 19.2overview ..............................................................................................................162 19.3ss pin functionality ............................................................................................167 19.4data modes .........................................................................................................167 19.5register description ............................................................................................169 20 usart0 .............. ................. .............. .............. .............. .............. .......... 172 20.1features ..............................................................................................................172 20.2overview ..............................................................................................................172 20.3clock generation .................................................................................................173 20.4frame formats ....................................................................................................176 20.5usart initialization .............................................................................................177 20.6data transmission ? the usart transmitter ....................................................179 20.7data reception ? the usart receiver .............................................................181 20.8asynchronous data reception ............................................................................185 20.9multi-processor communication mode ................................................................188 20.10examples of baud rate setting .........................................................................189 20.11register description ..........................................................................................194 21 usart in spi mode ............ .............. .............. .............. .............. .......... 199 21.1features ..............................................................................................................199 21.2overview ..............................................................................................................199 21.3clock generation .................................................................................................199 21.4spi data modes and timing ................................................................................200 21.5frame formats ....................................................................................................200 21.6data transfer .......................................................................................................203 v atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 21.7avr usart mspim vs. avr spi ......................................................................205 21.8register description ............................................................................................206 22 2-wire serial interface ..... ................. .............. .............. .............. .......... 209 22.1features ..............................................................................................................209 22.22-wire serial interface bus definition ..................................................................209 22.3data transfer and frame format ........................................................................210 22.4multi-master bus systems, arbitration and synchronization ...............................213 22.5overview of the twi module ...............................................................................215 22.6using the twi ......................................................................................................217 22.7transmission modes ...........................................................................................220 22.8multi-master systems and arbitration ..................................................................233 22.9register description ............................................................................................235 23 analog comparator ............ .............. .............. .............. .............. .......... 239 23.1overview ..............................................................................................................239 23.2analog comparator multiplexed input .................................................................239 23.3register description ............................................................................................240 24 analog-to-digital converter .............. .............. .............. .............. ........ 242 24.1features ..............................................................................................................242 24.2overview ..............................................................................................................242 24.3starting a conversion ..........................................................................................244 24.4prescaling and conversion timing ......................................................................245 24.5changing channel or reference selection .........................................................247 24.6adc noise canceler ...........................................................................................248 24.7adc conversion result .......................................................................................252 24.8temperature measurement .................................................................................252 24.9register description ............................................................................................254 25 debugwire on-chip debug syst em ............... .............. .............. ........ 259 25.1features ..............................................................................................................259 25.2overview ..............................................................................................................259 25.3physical interface ................................................................................................259 25.4software break points .........................................................................................260 25.5limitations of debugwire ...................................................................................260 25.6register description ............................................................................................260 26 self-programming the flash, atmega 48a/48pa ............. ................. 261 26.1overview ..............................................................................................................261 vi atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 26.2addressing the flash during self-programming .................................................262 26.3register description ............................................................................................267 27 boot loader support ? read-while-wri te self-programming ......... 269 27.1features ..............................................................................................................269 27.2overview ..............................................................................................................269 27.3application and boot loader flash sections .......................................................269 27.4read-while-write and no read-while-write flash sections ..............................269 27.5boot loader lock bits .........................................................................................272 27.6entering the boot loader program ......................................................................273 27.7addressing the flash during self-programming .................................................274 27.8self-programming the flash ................................................................................275 27.9register description ............................................................................................283 28 memory programming ........... ................. ................ ................. ............ 285 28.1program and data memory lock bits .................................................................285 28.2fuse bits ..............................................................................................................286 28.3signature bytes ...................................................................................................289 28.4calibration byte ...................................................................................................289 28.5page size ............................................................................................................290 28.6parallel programming parameters, pin mapping, and commands .....................290 28.7parallel programming ..........................................................................................292 28.8serial downloading ..............................................................................................299 29 electrical characteristics .. .............. .............. .............. .............. .......... 303 29.1absolute maximum ratings* ...............................................................................303 29.2dc characteristics ...............................................................................................303 29.3speed grades .....................................................................................................310 29.4clock characteristics ...........................................................................................311 29.5system and reset characteristics ......................................................................312 29.6spi timing characteristics ..................................................................................313 29.7two-wire serial interface characteristics ............................................................315 29.8adc characteristics ............................................................................................317 29.9parallel programming characteristics .................................................................318 30 electrical characteristics (ta = -40c to 105c) .... ................. .......... 320 30.1absolute maximum ratings* ...............................................................................320 30.2dc characteristics ...............................................................................................320 31 typical characteristics ...... .............. .............. .............. .............. .......... 324 vii atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 31.1atmega48a typical characteristics ...................................................................325 31.2atmega48pa typical characteristics .................................................................350 31.3atmega88a typical characteristics ...................................................................375 31.4atmega88pa typical characteristics .................................................................399 31.5atmega168a typical characteristics .................................................................425 31.6atmega168pa typical characteristics ...............................................................450 31.7atmega328 typical characteristics ....................................................................475 31.8atmega328p typical characteristics .................................................................500 32 atmega48pa typical charact eristics ? (ta = -40c to 105c) ........ 525 32.1active supply current ..........................................................................................525 32.2idle supply current ..............................................................................................528 32.3power-down supply current ................................................................................530 32.4power-save supply current .................................................................................531 32.5standby supply current ......................................................................................532 32.6pin pull-up ...........................................................................................................532 32.7pin driver strength ..............................................................................................535 32.8pin threshold and hysteresis ..............................................................................537 32.9bod threshold ....................................................................................................540 32.10internal oscilllator speed ..................................................................................542 32.11current consumption of peripheral units ..........................................................544 32.12current consumption in reset and reset pulsewidth ......................................547 33 atmega88pa typical charact eristics ? (ta = -40c to 105c) ........ 549 33.1active supply current ..........................................................................................549 33.2idle supply current ..............................................................................................552 33.3power-down supply current ................................................................................554 33.4power-save supply current .................................................................................555 33.5pin pull-up ...........................................................................................................556 33.6pin driver strength ..............................................................................................559 33.7pin threshold and hysteresis ..............................................................................561 33.8bod threshold ....................................................................................................564 33.9internal oscilllator speed ....................................................................................565 33.10current consumption of peripheral units ..........................................................568 33.11current consumption in reset and reset pulsewidth ......................................570 34 atmega168pa typical c haracteristics ? (ta = - 40c to 105c ) ...... 573 34.1active supply current ..........................................................................................573 34.2idle supply current ..............................................................................................576 viii atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 34.3power-down supply current ................................................................................578 34.4power-save supply current .................................................................................579 34.5standby supply current ......................................................................................580 34.6pin pull-up ...........................................................................................................580 34.7pin driver strength ..............................................................................................583 34.8pin threshold and hysteresis ..............................................................................585 34.9bod threshold ....................................................................................................588 34.10internal oscillator speed ...................................................................................591 34.11current consumption of peripheral units ..........................................................593 34.12current consumption in reset and reset pulsewidth ......................................596 35 atmega328p typical charact eristics ? (ta = -40 c to 105c) ........ 598 35.1atmega328p active supply current ...................................................................598 35.2idle supply current ..............................................................................................601 35.3power-down supply current ................................................................................603 35.4power-save supply current .................................................................................604 35.5standby supply current ......................................................................................605 35.6pin pull-up ...........................................................................................................605 35.7pin driver strength ..............................................................................................608 35.8pin threshold and hysteresis ..............................................................................610 35.9bod threshold ....................................................................................................613 35.10internal oscillator speed ...................................................................................615 35.11current consumption of peripheral units ..........................................................618 35.12current consumption in reset and reset pulsewidth ......................................620 36 register summary .............. .............. .............. .............. .............. .......... 622 37 instruction set summary ..... .............. .............. .............. .............. ........ 626 38 ordering information ........... .............. .............. .............. .............. ........ 629 38.1atmega48a ........................................................................................................629 38.2atmega48pa ......................................................................................................630 38.3atmega88a .........................................................................................................631 38.4atmega88pa ......................................................................................................632 38.5atmega168a .......................................................................................................633 38.6atmega168pa ...................................................................................................634 38.7atmega328 ........................................................................................................635 38.8atmega328p ......................................................................................................636 39 packaging information ......... .............. .............. .............. .............. ........ 637 ix atmega48a/pa/88a/pa/168a /pa/328/p [datasheet] 8271g?avr?02/2013 39.132a ......................................................................................................................6 37 39.232cc1 .................................................................................................................638 39.328m1 ....................................................................................................................63 9 39.432m1-a ................................................................................................................640 39.528p3 ....................................................................................................................64 1 40 errata ........... ................. ................ ................ ................. .............. .......... 642 40.1errata atmega48a ..............................................................................................642 40.2errata atmega48pa ...........................................................................................642 40.3errata atmega88a ..............................................................................................643 40.4errata atmega88pa ...........................................................................................643 40.5errata atmega168a ............................................................................................644 40.6errata atmega168pa .........................................................................................644 40.7errata atmega328 ..............................................................................................645 40.8errata atmega328p ............................................................................................646 41 datasheet revision history .. ............. .............. .............. .............. ........ 648 41.1rev. 8271g ? 02/2013 ........................................................................................648 41.2rev. 8271f ? 08/2012 .........................................................................................648 41.3rev. 8271e ? 07/2012 .........................................................................................648 41.4rev. 8271d ? 05/11 .............................................................................................649 41.5rev. 8271c ? 08/10 .............................................................................................649 41.6rev. 8271b ? 04/10 .............................................................................................649 41.7rev. 8271a ? 12/09 .............................................................................................650 table of contents ......... ................ ................ ................. ................ ............. i atmel corporation 1600 technology drive san jose, ca 95110 usa tel: (+1) (408) 441-0311 fax: (+1) (408) 487-2600 www.atmel.com atmel asia limited unit 01-5 & 16, 19f bea tower, millennium city 5 418 kwun tong roa kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan g.k. 16f shin-osaki kangyo bldg 1-6-4 osaki, shinagawa-ku tokyo 141-0032 japan tel: (+81) (3) 6417-0300 fax: (+81) (3) 6417-0370 ? 2012 atmel corporation. all rights reserved. / rev.: 8271g?avr?02/2013 disclaimer: the information in this document is provided in co nnection with atmel products. no lic ense, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. exc ept as set forth in the atmel terms and conditions of sales locat ed on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not li mited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any d irect, indirect, consequential, punitive, special or incide ntal damages (including, without limitation, damages for loss and profits, business i nterruption, or loss of information) arising out of the us e or inability to use this document, even if at mel has been advised of the possibility of suc h damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and products descriptions at any time without notice. atmel does not make any commitment to update th e information contained herein. un less specifically provided oth erwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel products are not intended, authorized, or warranted for use as components in applications intend ed to support or sustain life. atmel ? , atmel logo and combinations thereof, enabling unlimited possibilities ? , and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. |
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